Demodulator using digital circuitry

• US 6,639,459 B1
• Filed: 04/25/2002
• Issued: 10/28/2003
• Est. Priority Date: 04/25/2002
• Status: Expired due to Fees

• Current Assignee: Celis Semiconductor Corp.
• Original Assignee: Celis Semiconductor Corp.
• Inventors: Devilbiss, Alan D.
• Primary Examiner(s): Choe, Henry
• Application Number:
  US10/133,924
• Time in Patent Office: 551 Days
• Field of Search: 331/74, 329/341, 329/347, 329/351, 329/353, 329/370, 375/320
• US Class Current: 329/341
• CPC Class Codes: H03D 3/04 by counting or integrating cycles of oscillations arrangements for measuring frequencies G01R23/10

Abstract

A demodulator converts a voltage input to an output voltage. The demodulator has a voltage-controlled oscillator (VCO), a counter, a holding apparatus, and a digital compare apparatus. The VCO generates a signal having a frequency proportional to the analog input voltage. The counter counts each cycle of the signal generated by the VCO and outputs a count signal representative of the cycle count. The holding apparatus holds the count signal and generates a held count signal. The digital compare apparatus compares the count signal and the held count signal and generates the digital output.

Claims

1. A demodulator for converting an analog input voltage to an output voltage, the demodulator comprising:

(a) a voltage-controlled oscillator (VCO) configured to generate a signal having a frequency proportional to the analog input voltage;

(b) a counter configured to count each cycle of the signal generated by the VCO and output a count signal representative of the cycle count;

(c) a holding apparatus configured to hold the count signal and generate a held count signal and

(d) a digital compare apparatus configured to compare the count signal and the held count signal and generate the digital output.

2. The demodulator of claim 1 wherein the holding apparatus is selected from the group consisting of a flip-flop, a sample and hold circuit, a memory, and a latch.

3. The demodulator of claim 1 wherein the analog input voltage is proportional to a magnitude of a carrier signal modulated by a binary pattern and the output voltage includes a stream of binary data corresponding to the binary pattern that modulates the carrier signal.

4. A method for converting an analog input voltage to an output voltage, method comprising:

(a) generating a voltage signal having a frequency proportional to the analog input voltage source;

(b) counting the cycles of the voltage signal and generating a count signal representative of the cycle count;

(c) holding the count signal;

(d) resetting the cycle count;

(e) counting the cycles of the voltage signal and generating a count signal representative of the cycle count;

(f) comparing the count signal with the held count signal; and

(g) generating the output voltage from the comparison of the count signal with the held count signal.

5. The method of claim 4 wherein the count signal higher than the held count signal produces a positive transition in the output voltage.

6. The method of claim 4 wherein the count signal lower than the held count signal produces a negative transition in the output voltage.

7. The method of claim 4 wherein the count signal the same as the held count signal produces no transition in the output voltage.

8. The method of claim 4 wherein the analog input voltage is proportional to a magnitude of a carrier signal modulated by a binary pattern and generating the output voltage includes generating a stream of binary data corresponding to the binary pattern that modulates the carrier signal.

9. A demodulator for converting an analog input voltage to an output voltage, the demodulator supplied with a power supply voltage source and a reset clock, the demodulator comprising:

(a) a voltage-controlled oscillator (VCO) having an input terminal and an output terminal, the analog input voltage applied to the input terminal, the VCO configured to generate a signal having a frequency at the output terminal proportional to the analog input voltage source applied to the input terminal;

(b) a counter having an input terminal, an output terminal, and a reset terminal, the input terminal coupled to the output terminal of the VCO and the reset terminal connected to the reset clock;

(c) a holding apparatus having an input terminal, an output terminal, and a reset terminal, the input terminal connected to the output terminal of the counter and the reset terminal coupled to the reset clock; and

(d) a digital compare apparatus having first and second input terminals, an output terminal, and a reset terminal, the first input terminal connected to the output of the holding apparatus, the second input terminal connected to the output of the counter, and the reset terminal connected to the reset clock, the digital compare apparatus configured to provide the digital output at the output terminal.

10. The demodulator of claim 9 wherein the holding apparatus is selected from the group consisting of a flip-flop, a sample and hold circuit, a memory, and a latch.

11. The demodulator of claim 9 wherein the voltage controlled oscillator comprises:

(a) a Schmidt trigger having an input terminal, an output terminal, and a reset terminal, the reset terminal coupled to the reset clock;

(b) a storage capacitor having first and second terminals, the first terminal connected to the power supply source and the second terminal coupled to the input of the Schmidt trigger;

(c) a first transistor having a source terminal, a drain terminal, and a gate terminal, the drain terminal coupled to second terminal of the capacitor and the input of the Schmidt trigger, the source terminal coupled to ground, and the gate coupled to the input voltage; and

(d) a second transistor having a source terminal, a drain terminal, and a gate terminal, the drain terminal coupled to second terminal of the capacitor and the input of the Schmidt trigger, the source terminal coupled to power supply source, and the gate coupled to the output of the Schmidt trigger.

12. The demodulator of claim 9 wherein the analog input voltage is proportional to a magnitude of a carrier signal modulated by a binary pattern and the output voltage includes a stream of binary data corresponding to the binary pattern that modulates the carrier signal.