Semiconductor memory device having defective memory block

• US 6,639,858 B2
• Filed: 06/06/2002
• Issued: 10/28/2003
• Est. Priority Date: 07/09/2001
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Matsui, Hideo, Kinoshita, Hiromu
• Primary Examiner(s): Lam, David
• Application Number:
  US10/162,633
• Publication Number:
  US 20030007399A1
• Time in Patent Office: 509 Days
• Field of Search: 365/200, 365/230.03, 365/230.06, 365/225.7, 365/201, 365/230.08
• US Class Current: 365/200
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 29/883 using a single defective memory device with reduced capacity, e.g. half capacity

Abstract

A semiconductor memory such as 256 KB-memory has a memory cell array divided into a plurality of memory blocks, and a defective memory block exists in the memory cell array. In this case, to relive the 256 KB-memory as a 192 KB-memory not including the defective memory block of 64 KB, identification information identifying the defective memory block is stored in a relief condition storing unit, an address sent from an address bus is changed according to the identification information, and a changed address is input to a decoder of the memory cell array. For example, because a memory block of an address (0, 0) is not guaranteed, in cases where a physical address (0, 1) is assigned to the defective memory block, the address change is performed to change an address (0, 0) sent from the address bus to the address (0, 1 ) of the defective memory block.

Claims

1. A semiconductor memory comprising:

a memory cell array having a plurality of memory blocks;

identification information storing means for storing identification information which identifies a defective memory block existing in the memory blocks of the memory cell array; and

address changing means for receiving an address from an address bus, changing the address to a changed address according to the identification information of the identification information storing means and outputting the changed address to a decoder of the memory cell array to specify a memory cell of the memory cell array according to the changed address.

2. A semiconductor memory according to claim 1, wherein a usable memory capacity of the memory cell array is stored in the identification information storing means.

3. A semiconductor memory according to claim 2, wherein the identification information storing means is arranged in an area of a programmable read-only memory.

4. A semiconductor memory according to claim 2, wherein the identification information storing means is arranged in an area of a user read-only memory.

5. A semiconductor memory according to claim 2, wherein the identification information storing means is arranged in an area of a boot read-only memory.

6. A semiconductor memory according to claim 1, wherein the identification information storing means has a fuse corresponding to each of the memory blocks of the memory cell array, and the fuse corresponding to the defective memory block is cut.

7. A semiconductor memory according to claim 1, wherein the identification information stored in the identification information storing means is written on a chip of the semiconductor memory according to laser marking.

8. A semiconductor memory according to claim 1, wherein the address changing means comprises a logic circuit for receiving both an address signal indicating a value of an address bit of the address and a control signal controlling the address change, calculating an exclusive logical sum of both the address signal and the control signal and outputting the exclusive logical sum as the value of an address bit of the changed address.

9. A semiconductor memory according to claim 8, wherein the address changing means comprises a control signal producing circuit having a fuse for outputting the control signal, which indicates no change of the address in case of a non-cut fuse, to the logic circuit and outputting the control signal, which indicates a change of the address in case of a cut fuse, to the logic circuit.

10. A semiconductor memory according to claim 1, wherein the address changing means comprises a software tool so as to connect a plurality of memory blocks of the memory cell array other than the defective memory block according to a software process.

11. A semiconductor memory according to claim 1, wherein the address change is performed by the address changing means so as to change a specific address assigned to a bottom memory block to a physical address of the defective memory block identified by the identification information.