Method of screening non-volatile memory devices

• US 6,639,860 B2
• Filed: 02/06/2002
• Issued: 10/28/2003
• Est. Priority Date: 02/06/2002
• Status: Expired due to Fees

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Anzai, Yasuhito
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US10/066,748
• Publication Number:
  US 20030147294A1
• Time in Patent Office: 629 Days
• Field of Search: 365/201-211, 365/185.33, 438/15, 438/17, 714/718, 702/82, 702/117
• US Class Current: 365/201
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50016 of retention

Abstract

A method of screening for a non-volatile memory device, including the steps of: controlling the temperature of a memory device at a first level to carry out a first stage of screening; and then, controlling the temperature of a memory device at a second level, which is different from the first level to carry out a second stage of screening.

Claims

1. A method of screening a non-volatile memory device, comprising:

performing a first screening process to detect hopping conduction model defects controlling a temperature of the memory device at a first level; and

performing a second screening process, after said first screening process, to detect Arrhenius model defects by controlling the temperature of the memory device at a second level.

2. A method according to claim 1, wherein

the first level of temperature is lower than the second level of temperature.

3. A method according to claim 1, wherein

the memory device is a flash memory.

4. A method according to claim 1, wherein

the first level is lower than 150°

C.

5. A method according to claim 4, wherein

the first level is in a range of 70 to 150°

C.

6. A method according to claim 5, wherein

the second level of temperature is higher than 200°

C.

7. A method according to claim 5, wherein

the second level of temperature is around 250°

C.

8. A method of screening out a non-volatile memory device, comprising:

providing a semiconductor wafer including a plurality of flash memory devices thereon;

setting and leaving the wafer in a first thermostatic oven controlled in temperature in a range of 85 to 150°

C. for a predetermined period of time to carry out a first stage of screening;

taking out the wafer from the first thermostatic oven;

setting and leaving the wafer in a second thermostatic oven controlled in temperature at about 250°

C. for a predetermined period of time to carry out a second stage of screening;

taking out the wafer from the second thermostatic oven; and

cooling down the wafer at a room temperature.