Decoder circuit in a semiconductor memory device

• US 6,639,867 B2
• Filed: 03/26/2002
• Issued: 10/28/2003
• Est. Priority Date: 06/28/2001
• Status: Expired due to Fees

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Shim, Young Bo
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Yoha, Connie C.
• Application Number:
  US10/105,196
• Publication Number:
  US 20030002380A1
• Time in Patent Office: 581 Days
• Field of Search: 365/230.06, 365/230.08, 365/233, 365/185.23, 365/189.05
• US Class Current: 365/230.06
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A decoder circuit in a semiconductor memory device for improving the productivity of a semiconductor memory device by reducing the area occupied by a decoder. In order to accomplish this, a decoder circuit in a semiconductor memory device comprises a decoder control unit for receiving an external clock signal and a reset signal to generate a clear signal, an internal reset signal, a plurality of driver enable signals and a plurality of shift register enable signals; and a plurality of decoders for decoding the clear signal, the internal reset signal, the plurality of driver enable signals and the plurality of shift register enable signals to generate a plurality of wordline-driving signals.

Claims

1. A decoder circuit in a semiconductor memory device, the decoder circuit comprising:

a decoder control means for outputting a plurality of control signals in response to an external clock signal and a reset signal; and

a plurality of decoders each of which drives a plurality of word lines in response to the plurality of control signals, an output node of one decoder being connected to an input node of an adjacent decoder and an output node of a last decoder being connected to an input node of a first decoder.

2. The decoder circuit in a semiconductor memory device according to claim 1, wherein the decoder control means comprises:

a clear signal generator for receiving the external clock signal and an inverted signal of the reset signal to generate first and second internal clock signals and a clear signal;

an internal reset signal generator for receiving the reset signal to generate an internal reset signal;

an assembled latch circuit for generating a plurality of latch signals in response to the first and the second internal clock signals and the internal reset signal; and

a shift register/driver enable signal generator for receiving the plurality of latch signals to generate a plurality of driver enable signals and a plurality of shift register enable signals.

3. The decoder circuit in a semiconductor memory device according to claim 2, wherein the clear signal generator comprises:

a first logic device for logically combining the external clock signals and the inverted signal of the reset signal;

first and second inverting devices for inverting an output signal of the first logic device to generate the first internal clock signal;

a third inverting device for inverting the first internal clock signal to generate the second internal clock signal;

a second logic device for logically combining an inverted signal of the internal reset signal and the first internal clock signal; and

a plurality of inverting devices for inverting an output signal of the second logic device to generate the clear signal.

4. The decoder circuit in a semiconductor memory device according to claim 2, wherein the internal reset signal generator includes a plurality of inverting devices for sequentially inverting the reset signal to generate the internal reset signal.

5. The decoder circuit in a semiconductor memory device according to claim 2, wherein the assembled latch circuit has a loop structure in which an output signal of the latch circuit at the last stage of the plurality of latch circuits is inputted to the latch circuit at the first stage of the plurality of latch circuits.

6. The decoder circuit in a semiconductor memory device according to claim 5, wherein the assembled latch circuit includes a plurality of latch circuits for generating a plurality of latch signals in response to the first and the second internal clock signals and the internal reset signal.

7. The decoder circuit in a semiconductor memory device according to claim 2, wherein the shift register/driver enable signal generator comprises:

a plurality of driver enable signal generators for receiving the plurality of latch signals to generate the plurality of driver enable signals; and

a plurality of register enable signal generators for receiving some of the plurality of latch signals to generate the plurality of shift register enable signals.

8. The decoder circuit in a semiconductor memory device according to claim 2, wherein a decoder of the plurality of decoders comprises:

a shift register for generating a latch signal in response to the internal reset signal and the plurality of shift register enable signals, wherein the shift register is connected between the input node and the output node of the decoder; and

a plurality of drivers for receiving the latch signal, the plurality of driver enable signals and the clear signal to generate a plurality of word line-driving signals.

9. The decoder circuit in a semiconductor memory device according to claim 8, wherein the shift register in the first decoder comprises:

a first transfer unit for transferring an output signal from the output node of the last decoder of the plurality of the decoders in response to one of the plurality of shift register enable signals;

a first latch for latching a signal transferred from the first transfer unit in response to the internal reset signal;

a second transfer unit for transferring a signal latched by the first latch in response to another of the plurality of shift register enable signals;

a second latch for latching a signal transferred from the second transfer unit in response to the internal reset signal; and

a third transfer unit for transferring a signal latched by the second latch in response to the one of the plurality of shift register enable signals, wherein the latch signal is provided at the first latch.

10. The decoder circuit in a semiconductor memory device according to claim 8, wherein each of the plurality of drivers comprises:

a driving unit for receiving one of the plurality of latch signals and the clear signal to generate a driver-driving signal; and

a designated number of wordline-driving signal generators for receiving the driver-driving signal, the plurality of driver enable signals and the clear signal to generate some of the plurality of wordline-driving signals.

20. The decoder circuit in a semiconductor memory device according to claim 8, wherein the shift register in the last decoder comprises:

a first latch for latching a signal from the input node of the last decoder in response to the internal reset signal;

a transfer unit for transferring a signal latched by the first latch in response to one of the plurality of shift register enable signals; and

a second latch for latching a signal transferred from the transfer unit in response to the internal reset signal, wherein the latch signal is provided at the first latch.

21. The decoder circuit in a semiconductor memory device according to claim 8, wherein the shift register in a decoder between the first decoder and the last decoder comprises:

a first latch for latching a signal from the input node of the decoder in response to the internal reset signal;

a first transfer unit for transferring a signal latched by the first latch in response to one of the plurality of shift register enable signals;

a second latch for latching a signal transferred from the first transfer unit in response to the internal reset signal; and

a second transfer unit for transferring a signal latched by the second latch in response to another of the plurality of shift register enable signals, wherein the latch signal is provided at the first latch.

11. A decoder circuit in a semiconductor memory device, the decoder circuit comprising:

a decoder control means for generating an internal reset signal, a plurality of driver enable signals and a plurality of shift register enable signals in response to an external clock signal and a reset signal;

a plurality of shift registers for generating a plurality of latch signals in response to the internal reset signal and the plurality of shift register enable signals; and

a plurality of drivers for driving a plurality of wordlines in response to the plurality of latch signals and the plurality of driver enable signals,

wherein the plurality of shift registers has a loop structure in which an output signal of the shift register at the last stage of the plurality of shift registers is inputted to an input terminal of the shift register at the first stage of the plurality of shift registers.

12. The decoder circuit in a semiconductor memory device according to claim 11, wherein the decoder control means comprises:

a clear signal generator for receiving the external clock signal and an inverted signal of the reset signal to generate first and second internal clock signals and a clear signal;

an internal reset signal generator for receiving the reset signal to generate the internal reset signal;

an assembled latch circuit for generating a plurality of latch signals in response to the first and the second internal clock signals and the internal reset signal; and

a shift register/driver enable signal generator for receiving the plurality of latch signals to generate the plurality of driver enable signals and the plurality of shift register enable signals.

13. The decoder circuit in a semiconductor memory device according to claim 12, wherein the clear signal generator comprises:

a first logic device for logically combining the external clock signal and the inverted signal of the reset signal;

first and second inverting means for inverting an output signal of the first logic device to generate the first internal clock signal;

a third inverting device for inverting the first internal clock signal to generate the second internal clock signal;

a second logic device for logically combining the inverted signal of the internal reset signal and the first internal clock signal; and

a plurality of inverting means for inverting an output signal of the second logic device to generate the clear signal.

14. The decoder circuit in a semiconductor memory device according to claim 12, wherein the internal reset signal generator includes a plurality of inverting devices for sequentially inverting the reset signal to generate the internal reset signal.

15. The decoder circuit in a semiconductor memory device according to claim 12, wherein the assembled latch circuit has a loop structure in which an output signal of the latch circuit at the last stage of the plurality of latch circuits is inputted to the latch circuit at the first stage of the plurality of latch circuits.

16. The decoder circuit in a semiconductor memory device according to claim 15, wherein the assembled latch circuit includes a plurality of latch circuits for generating the plurality of latch signals in response to the first and the second internal clock signals and the internal reset signal.

17. The decoder circuit in a semiconductor memory device according to claim 12, wherein the shift register/driver enable signal generator comprises:

a plurality of driver enable signal generators for receiving the plurality of latch signals to generate the plurality of driver enable signals; and

a plurality of register enable signal generators for receiving some of the plurality of latch signals to generate the plurality of shift register enable signals.

18. The decoder circuit in a semiconductor memory device according to claim 11, wherein the plurality of shift registers comprise a plurality of following components arranged sequentially and repeatedly a predetermined number of times:

a first transfer unit for transferring the output signal from the shift register at the last stage in response to one of the plurality of shift register enable signals;

a first latch circuit for latching an output signal from the first transfer unit in response to the internal reset signal;

a second transfer unit for transferring the output signal of the first latch circuit in response to another of the plurality of shift register enable signals; and

a second latch circuit for latching an output signal from the second transfer unit in response to the internal reset signal.

19. The decoder circuit in a semiconductor memory device according to claim 11, wherein each of the plurality of drivers comprises:

a driving unit for receiving one of the plurality of latch signals and the clear signal to generate a driver-driving signal; and

a designated number of wordline-driving signal generators for receiving the driver-driving signal, the plurality of driver enable signals and the clear signal to generate some of the plurality of wordline-driving signals.

22. A decoder circuit in a semiconductor memory device comprising:

a plurality of decoders;

a decoder control means for controlling the plurality of decoders in response to an external clock signal and a reset signal, said plurality of decoders driving a plurality of word lines in response to output signals from said decoder control means;

said decoder control means including,

a clear signal generator for receiving the external clock signal and an inverted signal of the reset signal to generate first and second internal clock signals and a clear signal;

an internal reset signal generator for receiving the reset signal to generate an internal reset signal;

an assembled latch circuit for generating a plurality of latch signals in response to the first and the second internal clock signals and the internal reset signal; and

a shift register/driver enable signal generator for receiving the plurality of latch signals to generate a plurality of driver enable signals and a plurality of shift register enable signals.