Apparatus for data bus expansion between two instrument chassis

• US 6,640,273 B1
• Filed: 12/19/2000
• Issued: 10/28/2003
• Est. Priority Date: 01/05/2000
• Status: Expired due to Fees

• Current Assignee: Tektronix Incorporated (Fortive Corp.)
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Spisak, Kevin C., Hagen, Michael S.
• Primary Examiner(s): Lefkowitz, Sumati
• Application Number:
  US09/741,572
• Time in Patent Office: 1,043 Days
• Field of Search: 710/100, 710/300-304, 710/305, 710/104, 710/31, 710/8-19, 361/784-796, 361/803-810
• US Class Current: 710/104
• CPC Class Codes: G01R 31/2891 related to sensing or controlling of force, position, temperature G01R31/2874 takes precedence; sensing of force G01L; sensing of position G01B, G01D; sensing of temperature G01K; controlling in general G05
• CPC Class Codes: H05K 7/1459 Circuit configuration, e.g. routing signals

Abstract

Apparatus for data bus expansion between two instrument chassis comprises a first interface circuit, a connecting cable, and a second interface circuit. Detection circuitry in each interface circuit detects slot position. Slot position determines direction of address and data flow for each card. One of the first and second interface circuits is connected to a controller slot in a first chassis, and the other of the first and second interface circuits is connected to a non-controller slot in a second chassis. Bus interface circuitry for signal and identification are reconfigured in accordance with slot determination. As a result, the assembly formed by connection of two substantially identical interface cards with a cable, is symmetric and reversible.

Claims

1. An expanded address and data bus arrangement, comprising:

a first interface circuit coupled to a first chassis having a plurality of slot positions for receiving circuit cards;

a second interface circuit coupled to a second chassis having a plurality of slot positions for receiving circuit cards; and

a transmission line coupled between said first and second interface circuits;

said first interface circuit having detection circuitry for detecting its slot position and configuring its circuitry and direction of signal flow accordingly;

said second interface circuit having detection circuitry for detecting its slot position and configuring its circuitry and direction of signal flow accordingly;

said first and second interface circuits being substantially identical.

2. The expanded address and data bus arrangement of claim 1, wherein:

said detection circuitry detects an external signal from which slot position information can be derived.

3. The expanded address and data bus arrangement of claim 2, wherein:

said first interface circuit configures itself as a VXI slot 0 device or a VXI non-slot 0 device in response to a determination of which slot of a VXI chassis it occupies.

4. An expanded address and data bus arrangement, comprising:

a first interface circuit coupled to a first chassis having a plurality of slot positions for receiving circuit cards;

a second interface circuit coupled to a second chassis having a plurality of slot positions for receiving circuit cards; and

a cable coupled between said first and second interface circuits;

said first interface circuit having detection circuitry for detecting its slot position and configuring its circuitry and direction of signal flow accordingly;

said second interface circuit having detection circuitry for detecting its slot position and configuring its circuitry and direction of signal flow accordingly;

said first interface circuit, said cable, and said second interface circuit being coupled in that order to form an assembly, said assembly being symmetric and reversible.

5. The expanded address and data bus arrangement of claim 4, wherein:

said detection circuitry detects an external signal from which slot position information can be derived.

6. The expanded address and data bus arrangement of claim 5, wherein:

said first interface circuit configures itself as a VXI slot 0 device or a VXI non-slot 0 device in response to a determination of which slot of a VXI chassis it occupies.