Microprocessor with high-reliability operating mode
First Claim
1. A processor comprising:
- first and second execution clusters including a first plurality of execution resources and a second plurality of execution resources, respectively, of a plurality of execution units; and
an issue module to provide instructions to the first and second execution clusters, the issue module to provide different instructions to the first and second execution clusters when the processor is in a high-performance mode and to provide identical instructions to the first and second execution clusters when the processor is in a high reliability mode.
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Abstract
The present invention provides a processor capable of operating in high reliability and high performance modes in response to mode switch events. Execution resources of the processor are organized into multiple execution clusters. An issue unit provides different instructions to the execution clusters in high performance mode. The issue unit provides the same instructions to the execution clusters in high reliability mode and results generated by the different execution clusters are compared to detect soft errors. The processor may be switched between the high reliability and high performance mode under software control or in response to the detection of certain conditions, such as the execution of certain types of process threads. These include process threads from the operating system kernel, process threads comprising uncacheable instructions, and machine check process threads.
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Citations
23 Claims
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1. A processor comprising:
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first and second execution clusters including a first plurality of execution resources and a second plurality of execution resources, respectively, of a plurality of execution units; and
an issue module to provide instructions to the first and second execution clusters, the issue module to provide different instructions to the first and second execution clusters when the processor is in a high-performance mode and to provide identical instructions to the first and second execution clusters when the processor is in a high reliability mode. - View Dependent Claims (2)
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3. A processor comprising:
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first and second execution clusters; and
an issue module to provide instructions to the first and second execution clusters, the issue module to provide different instructions to the first and second execution clusters when the processor is in a high-performance (“
HP”
) mode and to provide identical instructions to the first and second execution clusters when the processor is in a high reliability (“
HR”
) mode, wherein the instructions are instruction bundles, each instruction bundle comprising one or more instruction syllables, wherein the issue module includes a dispersal module and the first and second execution clusters each includes a plurality of execution units, the dispersal module to direct an instruction syllable in the instruction bundles to one of the plurality of execution units in one or both of the execution clusters, according to whether the processor is in HP or HR mode, respectively.- View Dependent Claims (4, 5, 6, 7, 8, 9, 10)
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11. A computer system comprising:
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a memory to store a plurality of instructions, including a mode switch instruction; and
a processor including first and second execution clusters including a first plurality of execution resources and a second plurality of execution resources, respectively, of a plurality of execution units; and
an issue module to provide identical instructions to the first and second execution clusters when the processor is in a first mode and to provide different instructions to the first and second execution clusters when the processor is in a second mode, the processor switching between the first and second processor modes in response to the mode switch instruction. - View Dependent Claims (12, 13, 14)
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15. A computer system comprising:
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a memory to store a plurality of instructions, including a mode switch instruction; and
a processor including first and second execution clusters; and
an issue module to provide identical instructions to the first and second execution clusters when the processor is in a first mode and to provide different instructions to the first and second execution clusters when the processor is in a second mode, the processor switching between the first and second processor modes in response to the mode switch instruction, wherein the issue module includes a plurality of slots, the issue module to provide instructions from a first and second of the plurality of slots to the first and second execution clusters when the processor is in the second mode and to provide instructions from the first slot to the both the first and second execution clusters when the processor is in the first mode, wherein the mode switch instruction includes first and second mode switch instructions that set the execution mode status bit to first and second logic states, respectively, when the processor is to switch to the first and second execution modes; and
an execution mode status bit, wherein the issue module provides instructions to the execution clusters according to a logic state of the execution mode status bit. - View Dependent Claims (16, 17)
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18. A computer system comprising:
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a memory to store a plurality of instructions, including a mode switch instruction, and a processor including first and second execution clusters; and
an issue module to provide identical instructions to the first and second execution clusters when the processor is in a first mode and to provide different instructions to the first and second execution clusters when the processor is in a second mode, the processor switching between the first and second processor modes in response to the mode switch instruction, wherein the mode switch instruction comprises first and second mode switch instructions, the first mode switch instruction to write a first value to the execution mode status bit when the processor is to switch to the first execution mode, and the second mode switch instruction to write a second value to the execution mode status bit when the processor is to switch to the second execution mode; and
an execution mode status bit that indicates to the issue module whether the processor is in the first or second execution mode. - View Dependent Claims (19)
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20. A computer system comprising:
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a memory to store a process thread;
a processor including;
first and second execution clusters including a first plurality of execution resources and a second plurality of execution resources, respectively, of a plurality of execution units; and
an issue module to provide identical instructions to the first and second execution clusters when the processor is in a first mode and to provide different instructions to the first and second execution clusters when the processor is in a second mode, the processor to be switched between the first and second modes in response to a mode switch event. - View Dependent Claims (21, 22, 23)
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Specification