Method of manufacturing an integrated circuit with a dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers

• US 6,642,145 B1
• Filed: 08/22/2002
• Issued: 11/04/2003
• Est. Priority Date: 06/04/2001
• Status: Expired due to Term

• Current Assignee: Fullbrite Capital Partners, LLC
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Ngo, Minh Van, Wang, Pin-Chin Connie, Avanzino, Steven C.
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Smoot, Stephen W.
• Application Number:
  US10/226,520
• Time in Patent Office: 439 Days
• Field of Search: 438/637, 438/639, 438/645, 438/675, 438/686, 438/687, 438/688, 438/786
• US Class Current: 438/639
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76841 Barrier, adhesion or liner layers
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12044 OLED

Abstract

An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer formed over the semiconductor substrate has an opening provided therein. The dielectric layer is of non-barrier dielectric material capable of being changed into a barrier dielectric material. The dielectric layer around the opening is changed into the barrier dielectric material and the conductor core material is deposited to fill the opening. The conductor core is processed to form a channel for the integrated circuit.

Claims

1. A method of manufacturing an integrated circuit comprising:

providing a semiconductor substrate having a semiconductor device provided thereon;

forming a dielectric layer of non-barrier dielectric material capable of being reduced into a barrier dielectric material, the dielectric layer formed over the semiconductor substrate;

forming an opening in the non-barrier dielectric layer;

reducing the dielectric layer to change the non-barrier dielectric material around the opening to form a barrier dielectric material around the opening; and

depositing a conductor core over the dielectric layer to fill the opening and connect to the semiconductor device.

2. The method of manufacturing an integrated circuit as claimed in claim 1 wherein forming the dielectric layer uses SiCOH as the non-barrier dielectric material.

3. The method of manufacturing an integrated circuit as claimed in claim 1 wherein forming the dielectric layer uses SiCOH as the non-barrier dielectric material and changing the dielectric layer changes the SiCOH to SiC(H) as the barrier dielectric material.

4. The method of manufacturing an integrated circuit as claimed in claim 1 including depositing a change assisting material on the dielectric layer before depositing the conductor core.

5. The method of manufacturing an integrated circuit as claimed in claim 1 wherein depositing the conductor core deposits a material from a group consisting of copper, aluminum, gold, silver, a compound thereof, and a combination thereof.

6. A method of manufacturing an integrated circuit comprising:

providing a semiconductor substrate having a semiconductor device provided thereon;

forming a dielectric layer of non-barrier dielectric material capable of being reduced into a barrier dielectric material, the dielectric layer formed over the semiconductor substrate;

forming an opening in the non-barrier dielectric layer;

reducing the dielectric layer to change the non-barrier dielectric material around the opening to form a barrier dielectric material around the opening;

depositing a seed layer over the dielectric layer to line the opening;

depositing a conductor core over the seed layer to fill the opening and connect to the semiconductor device; and

planarizing the conductor core and the seed layer to form a channel.

7. The method of manufacturing an integrated circuit as claimed in claim 6 wherein forming the dielectric layer uses SiCOH as the non-barrier dielectric material.

8. The method of manufacturing an integrated circuit as claimed in claim 6 wherein forming the dielectric layer uses SiCOH as the non-barrier dielectric material and reducing the dielectric layer uses thermal treatment to reduce the SiCOH to SiC(H) as the barrier dielectric material.

9. The method of manufacturing an integrated circuit as claimed in claim 6 including depositing an atomic layer of oxygen-gettering material on the dielectric layer before depositing the seed layer.

10. The method of manufacturing an integrated circuit as claimed in claim 6 wherein depositing the seed layer and the conductor core deposits a material from a group consisting of copper, aluminum, gold, silver, a compound thereof, and a combination thereof.