Customizable and programmable cell array

• US 6,642,744 B2
• Filed: 10/05/2001
• Issued: 11/04/2003
• Est. Priority Date: 03/10/2000
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: eASIC Corporation (Intel Corporation)
• Inventors: Zeman, Richard, Cooke, Laurance, Wurman, Zeʼev, Or-Bach, Zvi
• Primary Examiner(s): Le, Don
• Application Number:
  US09/970,871
• Publication Number:
  US 20020043988A1
• Time in Patent Office: 760 Days
• Field of Search: 326/37-41
• US Class Current: 326/39
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

This invention discloses a customizable logic array including an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and customized interconnections providing permanent direct interconnections among at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.

Claims

1. A customizable logic array comprising:

an array of programmable cells is having a multiplicity of inputs and a multiplicity of outputs; and

customized interconnections providing permanent direct interconnections among at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs,

wherein said customized interconnections use at least three metal layers, wherein at least a majority of said metal layers constitutes repeated subpatterns, wherein at least two of said three metal layers comprise repeated subpatterns, and wherein

at least one of said three metal layers comprises a plurality of generally parallel bands extending parallel to a first axis, each band comprising a multiplicity of metal layer strips extending perpendicular to said first axis.

2. A customizable logic array according to claim 1, wherein

at least one of said three metal layers comprises a multiplicity of metal layer strips extending parallel to said first axis.

3. A customizable logic array comprising:

an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and

customized interconnections providing permanent direct interconnections among at least a plurality of said multiplicity of input and at least a plurality of said multiplicity of outputs,

wherein said customized interconnections use at least three metal layers, wherein at least a majority of said metal layers constitutes repeated subpatterns, wherein at least two of said three metal layers comprise repeated subpatterns, and wherein at least one of said three metal layers comprises a multiplicity of metal laser strips extending parallel to said first axis and also comprises a multiplicity of metal layer strips extending perpendicular to said first axis.

4. A customizable logic array comprising:

an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs, each of said programmable cells comprising at least one look-up table; and

customized interconnections providing permanent direct interconnections among at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs,

wherein;

at least some of said programmable cells are programmable by means of electrical signals supplied thereto;

at least some of said customized interconnections are customized by lithography carried out in the course of manufacture of said semiconductor customizable logic array; and

said at least one look-up table comprising;

at least two inputs; and

an electronic circuit which provides high speed response to changes in one of said two inputs with respect to the response time of changes to the other input.

5. A customizable logic array comprising:

an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs, each of said programmable cells including at least one simple logic gate selectably connected to at least one of said multiplicity of outputs; and

customized interconnections providing permanent direct interconnections among at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs, wherein said simple logic gate is a buffer.

6. A customizable logic array comprising:

an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs, each of said programmable cells including at least one simple logic gate selectably connected to at least one of said multiplicity of outputs; and

customized interconnections providing permanent direct interconnections among at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs, wherein said simple logic gate is an inverter.

7. A customizable logic array comprising:

an array of logic cell having a multiplicity of inputs and a multiplicity of outputs; and

customized interconnections permanently interconnecting at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs, wherein each of at least some of said logic cells comprises at least one flip-flop; and

a clock tree providing clock inputs to some of said flip-flops, wherein said clock tree provides a clock tree signal and an inverted clock tree signal, and wherein said clock tree comprises a power saving circuit to allow controlled connection between said clock tree signal and said inverted clock tree signal.

8. A semiconductor device comprising:

a plurality of logic cells having a multiplicity of inputs and a multiplicity of outputs, wherein each of at least some of said logic cells comprises at least one flip-flop; and

a clock tree providing clock inputs to some of said flip-flops, wherein said clock tree comprises a clock tree signal and an inverted clock tree signal, and wherein said clock tree comprises a power saving circuit to allow controlled connection between said clock tree signal and said inverted clock tree signal.

9. A customizable logic array comprising:

an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and

customized interconnections providing permanent direct interconnections among at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs, wherein said array of programmable cells is programmed at least twice, and wherein the effects of said programming at least twice on an output of said customizable logic array are examined.

10. A customizable logic array comprising:

array of logic cells having a multiplicity of inputs and a multiplicity of outputs;

at least first, second and third metal layers formed over said array of logic cells, said second metal layer comprising a plurality of generally parallel bands extending parallel to a first axis, each band comprising a multiplicity of second metal layer strips extending perpendicular to said first axis, and said first metal layer comprising a plurality of first metal layer strips extending perpendicular to a second axis; and

at least one via connecting at least one second metal layer strip with said first metal layer, said first metal layer underlying said second metal layer.

11. A customizable logic array according to claim 10, wherein

said at least first, second and third metal layers are part of a set of customized interconnections providing permanent direct interconnections among at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs.

12. A customizable logic array according to claim 11, wherein

said third metal layer comprises at least one third metal layer strip extending generally perpendicular to said second metal layer strips an being connected thereto by a via.

13. A customizable logic array according to claim 11, wherein

said third metal layer comprises at east one third metal layer strip extending generally parallel to said second metal layer strips and connecting two coaxial second metal layer strips by vias.

14. A customizable logic array according to claim 11, wherein

said second metal layer also comprises a multiplicity of second metal layer strips extending generally parallel to said first axis.

15. A customizable logic array according to claim 11, wherein

said logic cells are programmable logic cells.

16. A customizable logic array according to claim 11, wherein each of at least some of said logic cells comprises at least one look-up table.

17. A customizable logic array according to claim 16, each of the at least some of said logic cells also comprising at least one logic gate connected to at least one input of said look-up table.

18. A customizable logic array according to claim 11, wherein each of at least some of said logic cells includes at east one simple logic gate selectably connected to at least one of said multiplicity of outputs.

19. A customizable logic array according to claim 11, wherein each of at least some of said logic cells comprises at least one flip-flop.

20. A customizable logic array according to claim 19, also comprising a clock tree inputs to at least one of said flip-flops.

21. A customizable logic array according to claim 11, wherein

the functionality of said customizable logic array as being either logic or memory is determined by the configuration of said customize interconnections.

22. A customizable logic array according to claim 16, wherein

said look-up table comprises the following:

at least two inputs; and

an electronic circuit which provides high speed response to changes in one of said two inputs with respect to the response time of changes to the other input.

23. A customizable logic array according to claim 12, wherein

said logic cells are programmable logic cells.

24. A customizable logic array according to claim 13, wherein

said logic cells are programmable logic cells.

25. A customizable logic array according to claim 14, wherein

said logic cells are programmable logic cells.

26. A customizable logic array according to claim 12, wherein

said first metal layer comprises a repeating pattern.

27. A customizable logic array according to claim 26, wherein

said third metal layer comprises a repeating pattern.

28. A customizable logic array according to claim 12, and also comprising a custom via layer connecting said third metal layer to said second metal layer.

29. A customizable logic array according to claim 26, and also comprising a custom via layer connecting said third metal layer to said second metal layer.

30. A customizable logic array according to claim 28, wherein

said logic cells are programmable logic cells.

31. A customizable logic array according to claim 29, wherein

said logic cells are programmable logic cells.