Frequency detector for a phase locked loop system

• US 6,642,747 B1
• Filed: 03/15/2002
• Issued: 11/04/2003
• Est. Priority Date: 03/15/2002
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Chiu, Hon Kin
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Nguyen, Linh
• Application Number:
  US10/099,529
• Time in Patent Office: 599 Days
• Field of Search: 327/2, 327/3, 327/7, 327/8, 327/9, 327/12, 327/40, 327/41, 327/42, 327/43, 327/47, 327/49, 327/147, 327/156, 327/157, 327/163, 331/25, 331/DIG.2, 375/215, 375/375, 375/376
• US Class Current: 327/40
• CPC Class Codes: H03D 13/004 the logic means delivering pulses at more than one terminal, e.g. up and down pulses
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0893 the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/113 using frequency discriminator

Abstract

A frequency detector circuit is arranged to detect a frequency difference between a clock signal and a reference clock signal. The frequency detector circuit includes four flip-flop circuits and a clear logic circuit. The clear logic circuit is arranged to clear selected flip-flop circuits. Two of the flip-flop circuits are arranged to detect two consecutive transitions in the clock signal without a clearing signal to provide a DOWN signal. The other two flip-flop circuits are arranged to detect two consecutive transitions in the reference clock signal without a clearing signal to provide an UP signal. The average of the UP and DOWN signals over a time interval corresponds to the difference in frequency between the clock signal and the reference clock signal. The UP and DOWN signals provide signals that may be employed by a charge pump circuit in a phase-locked-loop system to adjust the frequency of a VCO.

Claims

1. An apparatus for detecting a difference in frequencies between a first input signal and a second input signal, comprising:

a clear logic circuit that is arranged to activate a clear signal when a first intermediate signal and a second intermediate signal correspond to a first logic level, and arranged to deactivate the clear signal when at least one of the first intermediate signal and the second intermediate signal corresponds to a second logic level, wherein the second logic level is an inverse of the first logic level, wherein the clear logic circuit comprises;

a delay circuit that includes an input terminal and an output terminal;

a NAND logic circuit that has an input terminal that is coupled to the first intermediate signal, another input terminal that is coupled to the second intermediate signal, and an output terminal that is coupled to the input terminal of the delay circuit; and

an inverter circuit that includes an input terminal that is coupled to the output terminal of the delay circuit, and an output terminal that is configured to provide the clear signal;

a first flip-flop circuit that is arranged to set the first intermediate signal to the first logic level in response to the first input signal when the clear signal is deactivated, and arranged to reset the first intermediate signal to the second logic level when the clear signal is activated;

a second flip-flop circuit that is arranged to set the second intermediate signal to the first logic level in response to the second input signal when the clear signal is deactivated, and arranged to reset the second intermediate signal to the second logic level when the clear signal is activated;

a third flip-flop circuit that is arranged to activate an up signal in response to the first input signal when the first intermediate signal corresponds to the first logic level, such that the up signal is activated when the first input signal pulses twice before the clear signal is activated; and

a fourth flip-flop circuit that is arranged to activate a down signal in response to the second input signal when the second intermediate signal corresponds to the first logic level, such that the down signal is activated when the second input signal pulses twice before the clear signal is activated, wherein the up and down signals are related to the difference in frequencies between the first input signal and the second-input signal.

2. An apparatus as in claim 1, wherein the first flip-flop circuit, the second flip-flop circuit, the third flip-flop circuit, and the fourth flip-flop circuit correspond to D-type flip-flop circuits.

3. An apparatus as in claim 1, wherein the clear logic circuit further comprises an AND logic circuit.

4. An apparatus as in claim 1, the clear logic circuit further comprising a delay circuit that includes an input terminal and an output terminal, wherein the delay circuit has a transport delay that is associated with a change in a logic signal at the input terminal and a change in another logic signal at the output terminal such that the clear signal is activated for a minimum pulse-width that is related to the transport delay.

5. An apparatus as in claim 1, the clear logic circuit further comprising a multiplexer circuit that includes an input terminal that is coupled to the output terminal of the inverter circuit, another input terminal that is coupled to a power supply signal, a select terminal that is coupled to a reset signal, and an output terminal that is configured to provide the clear signal by selecting between the power supply signal and the output terminal of the inverter circuit in response to the reset signal.

7. An apparatus as in claim 1, wherein the first, second, third, and fourth flip-flop circuits are arranged-such that the up and down signals correspond to low logic levels when the frequencies of the first and second input signals are matched.

8. An apparatus as in claim 1, wherein the first, second, third, and fourth flip-flop circuits are arranged such that the down signal corresponds to a low logic level, and the up signal has an average logic level (AVG_UP) that is given by:

 

AVG_UP=1−

(f2/f1),

where f1 corresponds to the frequency of the first input signal, f2 corresponds to the frequency of the second input signal, and f1>

f2.

9. An apparatus as in claim 1, wherein the first, second, third, and fourth flip-flop circuits are arranged such that the up signal corresponds to a low logic level, and the down signal has an average logic level (AVG_DOWN) that is given by:

6. An apparatus for detecting a difference in frequencies between a first input signal and a second input signal, comprising:

a clear logic circuit that is arranged to activate a clear signal when a first intermediate signal and a second intermediate signal correspond to a first logic level, and arranged to deactivate the clear signal when at least one of the first intermediate signal and the second intermediate signal corresponds to a second logic level, wherein the second logic level is an inverse of the first logic level;

a first flip-flop circuit that is arranged to set the first intermediate signal to the first logic level in response to the first input signal when the clear signal is deactivated, and arranged to reset the first intermediate signal to the second logic level when the clear signal is activated;

a second flip-flop circuit that is arranged to set the second intermediate signal to the first logic level in response to the second input signal when the clear signal is deactivated, and arranged to reset the second intermediate signal to the second logic level when the clear signal is activated;

a third flip-flop circuit that is arranged to activate an up signal in response to the first input signal when the first intermediate signal corresponds to the first logic level, such that the up signal is activated when the first input signal pulses twice before the clear signal is activated;

a fourth flip-flop circuit that is arranged to activate a down signal in response to the second input signal when the second intermediate signal corresponds to the first logic level, such that the down signal is activated when the second input signal pulses twice before the clear signal is activated, wherein the up and down signals are related to the difference in frequencies between the first input signal and the second input signal; and

a first delay circuit that is arranged to provide the first intermediate signal to the third flip-flop circuit after a predetermined delay, and a second delay circuit that is arranged to provide the second intermediate signal to the fourth flip-flop circuit after another predetermined delay, such that the third and fourth flip-flop circuits have stable input signals when the first and second input signals transition.

10. An apparatus for detecting a difference between a frequency that is associated with a clock signal and a frequency that is associated with a reference clock signal, comprising:

a first means for detecting a transition in the reference clock signal and providing a first intermediate signal that has a first logic level;

a second means for detecting a transition in the clock signal and providing a second intermediate signal that has a first logic level;

a means for resetting arranged to provide a clear signal when the first and second intermediate signals correspond to the first logic level, such that the clear signal sets the first and second intermediate signals to a second logic level when the clear signal is asserted, wherein the second logic level is an inverse of the first logic level;

a first means for delaying that is arranged to provide a first delayed signal in response to the first intermediate signal, wherein the first delayed signal is related to the first intermediate signal according to a delay factor;

a third means for receiving the first delayed signal and detecting a transition in the reference clock signal to provide an up signal when the reference clock pulses at least twice without asserting the clear signal;

a fourth means for receiving the second intermediate signal and detecting a transition in the clock signal to provide a down signal when the reference clock pulses at least twice without asserting the clear signal.

11. An apparatus for detecting a difference between a frequency that is associated with a clock signal and a frequency that is associated with a reference clock signal, comprising:

a first means for detecting a transition in the reference clock signal and providing a first intermediate signal that has a first logic level;

a second means for detecting a transition in the clock signal and providing a second intermediate signal that has a first logic level;

a means for resetting arranged to provide a clear signal when the first and second intermediate signals correspond to the first logic level, such that the clear signal sets the first and second intermediate signals to a second logic level when the clear signal is asserted, wherein the second logic level is an inverse of the first logic level;

a second means for delaying that is arranged to provide a second delayed signal in response to the second intermediate signal, wherein the second delayed signal is related to the second intermediate signal according to a delay factor;

a third means for receiving the first intermediate signal and detecting a transition in the reference clock signal to provide an up signal when the reference clock pulses at least twice without asserting the clear signal; and

a fourth means for receiving the second delayed signal and detecting a transition in the clock signal to provide a down signal when the reference clock pulses at least twice without asserting the clear signal.

12. A phase-locked-loop system, comprising:

a voltage controlled oscillator that is arranged to provide a VCO clock signal, wherein the VCO clock signal has a corresponding frequency of f2 that is adjusted in response to a VCO input signal;

a phase detector circuit that provides a first up signal and a first down signal in response to a reference clock signal and the VCO clock signal, wherein the reference clock signal has a corresponding frequency of f1, wherein the phase detector circuit comprises;

a first NAND logic circuit that is arranged to provide the first up signal in response to the reference clock signal and an inverse of the VCO clock signal;

a second NAND logic circuit that is arranged to provide the first down signal in response to the reference clock signal an the VCO clock signal; and

an inverter circuit that is arranged to provide the inverse of the VCO clock signal in response to the VCO clock signal;

a first charge-pump circuit that is arranged to provide a first current in response to the first up signal and the first down signal;

a frequency detector circuit that provides a second up signal and a second down signal in response to the reference clock signal and the VCO clock signal, wherein an average logic level of the second up signal corresponds to zero when f2≧

f1, the average logic level of the second up signal corresponds to (1−

(f2/f1)) when f1>

f2, an average logic level of the second down signal corresponds to zero when f1≧

f2, and an average logic level of the second down signal corresponds to (1−

(f1/f2)) when f2>

f1;

a second charge-pump circuit that is arranged to provide a second current in response to the second up signal and the second down signal such that the second current has an average value that is related to the average logic levels of the second up signal and the second down signal; and

a capacitor circuit that is arranged to provide the VCO input signal in response to the first current and the second current, wherein the frequency detector circuit is arranged to acquire a frequency lock between the reference clock signal and the VCO clock signal, and the phase detector circuit is arranged to adjust the phase between the reference clock signal and the VCO clock signal.

13. A phase-locked-loop system as in claim 12, the frequency detector circuit comprising:

a clear logic circuit that is arranged to activate a clear signal when a first intermediate signal and a second intermediate signal correspond to a first logic level, and arranged to deactivate the clear signal when at least one of the first intermediate signal and the second intermediate signal corresponds to a second logic level, wherein the second logic level is an inverse of the first logic level;

a first flip-flop circuit that is arranged to set the first intermediate signal to the first logic level in response to the reference clock signal when the clear signal is deactivated, and arranged to reset the first intermediate signal to the second logic level when the clear signal is activated;

a second flip-flop circuit that is arranged to set the second intermediate signal to the first logic level in response to the VCO clock signal when the clear signal is deactivated, and arranged to reset the second intermediate signal to the second logic level when the clear signal is activated;

a third flip-flop circuit that is arranged to activate an up signal in response to the reference clock signal when the first intermediate signal corresponds to the first logic level, such that the up signal is activated when the reference clock signal pulses twice before the clear signal is activated; and

a fourth flip-flop circuit that is arranged to activate a down signal in response to the VCO clock signal when the second intermediate signal corresponds to the first logic level, such that the down signal is activated when the VCO clock signal pulses twice before the clear signal is activated, wherein the up and down signals are related to the difference in frequencies-between the reference clock signal and the VCO clock signal.

14. A phase-locked-loop system as in claim 12, wherein the phase detector circuit is arranged to adjust a phase between the reference clock signal and the VCO clock signal such that there is a constant phase difference between the reference clock signal and the VCO clock signal.