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Frequency detector for a phase locked loop system

  • US 6,642,747 B1
  • Filed: 03/15/2002
  • Issued: 11/04/2003
  • Est. Priority Date: 03/15/2002
  • Status: Active Grant
First Claim
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1. An apparatus for detecting a difference in frequencies between a first input signal and a second input signal, comprising:

  • a clear logic circuit that is arranged to activate a clear signal when a first intermediate signal and a second intermediate signal correspond to a first logic level, and arranged to deactivate the clear signal when at least one of the first intermediate signal and the second intermediate signal corresponds to a second logic level, wherein the second logic level is an inverse of the first logic level, wherein the clear logic circuit comprises;

    a delay circuit that includes an input terminal and an output terminal;

    a NAND logic circuit that has an input terminal that is coupled to the first intermediate signal, another input terminal that is coupled to the second intermediate signal, and an output terminal that is coupled to the input terminal of the delay circuit; and

    an inverter circuit that includes an input terminal that is coupled to the output terminal of the delay circuit, and an output terminal that is configured to provide the clear signal;

    a first flip-flop circuit that is arranged to set the first intermediate signal to the first logic level in response to the first input signal when the clear signal is deactivated, and arranged to reset the first intermediate signal to the second logic level when the clear signal is activated;

    a second flip-flop circuit that is arranged to set the second intermediate signal to the first logic level in response to the second input signal when the clear signal is deactivated, and arranged to reset the second intermediate signal to the second logic level when the clear signal is activated;

    a third flip-flop circuit that is arranged to activate an up signal in response to the first input signal when the first intermediate signal corresponds to the first logic level, such that the up signal is activated when the first input signal pulses twice before the clear signal is activated; and

    a fourth flip-flop circuit that is arranged to activate a down signal in response to the second input signal when the second intermediate signal corresponds to the first logic level, such that the down signal is activated when the second input signal pulses twice before the clear signal is activated, wherein the up and down signals are related to the difference in frequencies between the first input signal and the second-input signal.

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