Broadband sample and hold circuit

• US 6,642,752 B1
• Filed: 09/20/2002
• Issued: 11/04/2003
• Est. Priority Date: 09/20/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Nagaraj, Krishnasawamy
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US10/251,425
• Time in Patent Office: 410 Days
• Field of Search: 327/91-96, 341/122
• US Class Current: 327/94
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence

Abstract

A sample and hold device is provided in which sample switches are employed to switch between a sample phase and a hold phase. The sample and hold device provides alternate paths for the AC currents flowing to and from the sampling capacitor during the sample phase to mitigate the deleterious effects of the high AC currents through sample switches. The current drawn by the sampling capacitor from the input signal is replicated and directed to charge and discharge the sampling capacitor through alternate paths with respect to a path through the sample switches.

Claims

1. A sample and hold device comprising:

a sampling capacitor coupled at a first end to an input terminal through an input sample switch and a second end to a ground, the sampling capacitor operative to receive a voltage input signal at the input terminal during a sample chase and charge to a voltage amplitude level of the input signal that is held by the sampling capacitor during a hold phase; and

a current mirror that generates a current that is a replicate of a current drawn by the sampling capacitor during the sample phase and steers the replicated current through an alternate path with respect to a path through the input sample switch to the first end of the capacitor to mitigate the current flowing through the input sample switch; and

wherein the second end of the capacitor is coupled to ground through a ground sample switch and a second current mirror that generates a second current that replicates a current drawn by the sampling capacitor during the sample phase and steers the second replicated current through an alternate path with respect to a path through the ground sample switch to remove current from the second end of the sampling capacitor to mitigate the current flowing through the ground sample switch.

2. The device of claim 1, the voltage input signal being a differential input signal such that the current mirror receives a positive rail voltage input signal and the second current mirror receives a negative rail voltage input signal.

3. The device of claim 1, further comprising an inverted amplifier that provides an inverted version of the voltage input signal to the second current mirror.

4. The device of claim 1, the input sample switch and the ground sample switch being MOSFET devices.

5. The device of claim 1, the second current mirror cooperates with a current source to direct the second replicated current from the second end of the sampling capacitor.

6. The device of claim 1, the second current mirror comprising a capacitor having a capacitive value substantially equivalent to the sampling capacitor, such that the capacitor draws current substantially equivalent to current drawn by the sampling capacitor.

7. A sample and hold device comprising:

a sampling capacitor coupled at a first end to an input terminal through an input sample switch and a second end to a around the sampling capacitor operative to receive a voltage input signal at the input terminal during a sample phase and charge to a voltage amplitude level of the input signal that is held by the sampling capacitor during a hold phase; and

a current mirror that generates a current that is a replicate of a current drawn by the sampling capacitor during the sample phase and steers the replicated current through an alternate path with respect to a path through the input sample switch to the first end of the capacitor to mitigate the current flowing through the input sample switch; and

wherein the current mirror comprises a capacitor having a capacitive value substantially equivalent to the sampling capacitor, such that the capacitor draws current substantially equivalent to current drawn by the sampling capacitor.

8. The device of claim 7, the current mirror further comprising a cascade pair coupled to the capacitor.

9. A sample and hold device comprising:

a sampling capacitor coupled at a first end to an input terminal through an input sample switch and a second end to a ground, the sampling capacitor operative to receive a voltage input signal at the input terminal during a sample phase and charge to a voltage amplitude level of the input signal that is held by the sampling capacitor during a hold phase; and

a current mirror that generates a current that is a replicate of a current drawn by the sampling capacitor during the sample phase and steers the replicated current through an alternate path with respect to a path through the input sample switch to the first end of the capacitor to mitigate the current flowing through the input sample switch; and

wherein the current mirror directs the replicated current into the first end of the sampling capacitor.

10. A sample and hold circuit comprising:

a sampling capacitor coupled at a first end to an input terminal through an input sample switch and a second end coupled to a ground through a ground sample switch, the sampling capacitor operative to receive a voltage input signal at the input terminal during a sample phase and charge to a voltage amplitude level of the input signal that is held by the sampling capacitor during a hold phase;

a first capacitor that draws a first current along a first alternate path with respect to a path through the input sample switch, the first current is a substantial replicate of a current required to charge the sampling capacitor during the sample phase, the first current being directed into the first end of the sampling capacitor to mitigate the current flowing through the input sample switch; and

a second capacitor that draws a second current along a second alternate path with respect to a path through the ground sample switch, the second current is a substantial replicate of a current required to charge the sampling capacitor during the sample phase, the second current being directed out of the second end of the sampling capacitor to mitigate the current flowing through the ground sample switch.

11. The circuit of claim 10, the first capacitor being part of a first current mirror and the second capacitor being part of a second current mirror, the first capacitor receives a positive version of the voltage input signal and the second capacitor receives an inverted version of the voltage input signal, such that the first current mirror steers the first current Into the first end of the sampling capacitor and the second current mirror steers the second current from the second end of the sampling capacitor.

12. The circuit of claim 11, the first current mirror cooperates with a first current source to direct current into the first end of the sampling capacitor and the second current mirror cooperates with a second current source to direct current from the second end of the sampling capacitor.

13. The circuit of claim 10, the voltage input signal being a differential signal such that the positive rail of the differential signal is provided to the first capacitor and the negative rail of the differential signal is provided to the second capacitor.

14. The circuit of claim 10, further comprising an inverting amplifier that receives the positive version of the voltage input signal and provides the negative version of the voltage input signal.

15. The circuit of claim 10, the input sample switch and the ground sample switch being MOSFET devices.

16. A method for operating a sample and hold device having an input sampling switch that couples a first end of a sampling capacitor to an input voltage signal and a hold switch that couples the sampling capacitor to an output terminal, the method comprising:

receiving an input voltage signal;

opening the hold switch and closing the input sample switch to couple the sampling capacitor to the input voltage signal;

generating a first current that replicates a current required to charge the sampling capacitor to a voltage amplitude level of the input voltage signal;

directing the first current through an alternate path with respect to a path through the input sample switch into the first end of the sampling capacitor to mitigate current through the input sample switch; and

closing the hold switch and opening the input sample switch to couple the sampling capacitor to the output terminal.

17. The method of claim 16, further comprising generating a second current that replicates a current required to charge the sampling capacitor to a voltage amplitude level of the input voltage signal, and directing the second current from a second end of the sampling capacitor to mitigate current through a ground sample switch that couples a second end of the sampling capacitor to ground.

18. The method of claim 17, further comprising employing an inverted version of the input voltage signal in generating the second current.

19. The method of claim 17, the first current being generated by a current mirror having a first capacitor and the second current being generated by a current mirror having a second capacitor, the first capacitor and the second capacitor having capacitive values substantially equivalent to the sampling capacitor.

20. A sample and hold device having an input sampling switch that couples a first end of a sampling capacitor to an input voltage signal and a ground sampling switch that couples a second end of the sampling capacitor to ground, the device comprising:

means for providing current that replicates a current required to charge the sampling capacitor to a voltage amplitude level of the input voltage signal to the first end of the sampling capacitor through an alternate path with respect to a path through the input sampling switch; and

means for discharging current that replicates a current required to charge the sampling capacitor to a voltage amplitude level of the input voltage signal from the second end of the capacitor through an alternate path with respect to a path through the ground sampling switch.

21. The device of claim 20, the means for providing current comprising means for generating a first current and means for steering the first current to the first end of the capacitor through an alternate path with respect to a path through the input sampling switch.

22. The device of claim 20, the means for discharging current comprising means for generating a second current and means for steering the second current from the second end of the capacitor through an alternate path with respect to a path through the ground sampling switch.

23. The device of claim 20, the input sample switch and the ground sample switch being MOSFET devices and the input voltage signal being a continuous time-varying amplitude input signal.

24. The device of claim 23, the continuous time-varying amplitude input signal being a differential input signal, the means for providing current employing a positive rail of the input voltage signal to replicate the current and the means for discharging employing a negative rail of the input voltage signal to replicate the current.