Method for encoding/decoding digital data transmitted through a serial link, particularly of the 8B/10 type, and device for implementing same

• US 6,642,862 B2
• Filed: 12/05/2001
• Issued: 11/04/2003
• Est. Priority Date: 12/05/2000
• Status: Expired due to Term

• Current Assignee: Bull Sas (Atos SE)
• Original Assignee: Bull Sas (Atos SE)
• Inventors: Boudry, Jean-Marie
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Mai, Lam T.
• Application Number:
  US10/002,139
• Publication Number:
  US 20020109616A1
• Time in Patent Office: 699 Days
• Field of Search: 341/58, 341/59, 341/95, 709/231, 370/535
• US Class Current: 341/58
• CPC Class Codes: H03M 13/31 combining coding for error detection or correction and efficient use of the spectrum without error detection or correction H03M5/14 , H03M5/145
• CPC Class Codes: H03M 5/145 Conversion to or from block codes or representations thereof

Abstract

A method and a device is disclosed for encoding/decoding digital data transmitted through a serial link, particularly of the so-called “8B/10B” type. A full encoded binary word includes 8 data bits and a 2-bit label. The logical state of a center bit triplet of the byte is detected. When all of the bits are in the same logical state, the center bit of the triplet is inverted prior to transmission. Otherwise, the byte is transmitted as is. The label is forced to the logical configuration “10” when there is a bit inversion, and to “01” in the opposite case. Upon decoding, this configuration is tested and the center bit received is selectively inverted as a function of the result of the test. In a preferred variant, the method also includes tests of the label and the triplet after decoding, when there has been a bit inversion in the encoding. The device comprises logical circuits based on inverters and “AND,” “OR” and “EXCLUSIVE-OR” logic gates.

Claims

1. A method for encoding/decoding digital data to be transmitted through a serial link, said digital data comprising a first data bit sequence and a second label bit sequence, said first and second sequences having first (m) and second (p) given bit lengths, said method comprising:

an encoding phase comprising checking at least one slice of at least two consecutive bits, each of said slices being located in a predetermined area of said first bit sequence, so as to create a partitioning of the latter into parts of approximately equal length, said checking step including performing a test to determine whether the consecutive bits of each of said slices are in a same logical state, setting the bits of said second sequence to predetermined logical state configurations in one-to-one relation with a result of said test, and inverting at least one bit of said slices when the result of said test is positive and transmitting said first bit sequence without any modifications when the result of said test is negative.

2. The method according to claim 1, wherein the number of bits (p) in said second sequence is greater than or equal to the number of said slices (t).

3. The method according to claim 1, wherein said encoding is of an “

8B/10W”

type, said first sequence having a length of 8 bits so as to form a data byte, wherein successive positions are numbered 1 through 8, wherein said second sequence has a length of 2 bits, and wherein said method further comprises checking a 3-bit slice that includes bit number 5, said bits of said second sequence being set to a logical configuration “

10”

when the result of said check indicates that said three bits of said slice are in the same logical state and in the logical configuration “

01”

in the opposite case.

4. The method according to claim 1, further comprising:

a decoding phase for decoding said encoded digital data comprising at least one step for checking the logical state configuration of the bits of said second sequence and a step for selectively inverting at least one bit of said slices upon detection, during said check, of predetermined logical configurations of said second sequence, in order to re-establish said first sequence in its original state.

5. The method according to claim 4, wherein said logical configurations that can be assumed by the bits of said second sequence are included in a first subset of all possible combinations permitted by the number of bits constituting this sequence, and wherein said method further includes detecting non-permitted logical state configurations, constituted by a second subset, the counterpart of the first, indicating at least one error occurring in said second sequence.

6. The method according to claim 4, wherein when said step for checking the logical state configuration of the bits of said second sequence indicates the presence of a bit inversion during the encoding, in at least one of said slices, an additional step after decoding is performed which includes verifying that all the bits of said slice are in the same logical state.

7. A device for encoding/decoding digital data to be transmitted through a serial link, said digital data comprising a first data bit sequence and a second label bit sequence, said first and second sequences having first (m) and second (p) given bit lengths, said device comprising:

an encoder having at least one first element for checking at least one slice of at least two consecutive bits, each of said slices located in a predetermined area of said first bit sequence, so as to create a partitioning of the latter into parts of approximately equal length, said first element performing a test to determine whether consecutive bits of each of said slices are in a same logical state, and delivering an output signal at an output in a first given logical state when said test is positive and in a second given logical state when said test is negative,

a second element having a first and second input, said second element receiving the output signal from said first element through the first input and a given bit of said slices through the second input, so as to transmit it unchanged when said test is negative and to invert it when said test is positive, and

a third element driven by said output signal for generating predetermined logical configurations, in one-to-one relation.

8. The device according to claim 7, wherein said encoding is an “

8B/10B”

type, wherein said first sequence has a length of 8 bits so as to form a data byte (A . . . H), wherein successive positions are numbered 1 through 8, said second sequence having a length of 2 bits, wherein said slice has a length of 3 bits,

wherein said first element comprises an “

AND”

logic gate and an “

OR”

logic gate in parallel, each with three inputs, in order to receive through each of their inputs one of the 3 bits of said slice that includes bit number 5, and an “

OR”

logic gate with two inputs, receiving the output signal directly from said “

AND”

logic gate and receiving via an inverter the output signal from said “

OR”

logic gate, in order to deliver as output a signal in the logical state “

1”

if, and only if, all the bits of said slice are in the same logical state,

wherein said second element is an “

EXCLUSIVE-OR”

logic gate with two inputs, receiving through a first input the output signal from said first element, and through a second input the center bit of said 3-bit slice, so as to transmit it unchanged when said test is negative and to invert it when said test is positive, and

wherein said third element comprises an inverter receiving as input said output signal from said first element, said second sequence being constituted by a first bit in the same logical state as this signal and a second bit in the same logical state as the output signal from said inverter.

9. The device according to claim 7, further comprising:

a decoder comprising at least one checking element for checking the configuration of the bits of said second sequence in order to selectively invert at least one bit of said slices upon detection of given configurations indicating that this bit has been inverted during the encoding and to re-establish said first sequence in its original state.

10. The device according to claim 9, wherein the encoder is an “

8B/10B”

type, wherein said first sequence has a length of 8 bits so as to form a data byte, wherein successive positions are numbered 1 through 8, said second sequence having a length of 2 bits, wherein said slice has a length of 3 bits, said checking element comprising an “

AND”

logic gate having a direct input and an inverting input, the bits of said second sequence being transmitted to these respective inputs, and

wherein an “

EXCLUSIVE-OR”

logic gate with two inputs receives through a first input the output signal from said “

AND”

logic gate, and through a second input the center bit (D′

) of said three-bit slice, in order to transmit it unchanged when the logical configuration of said second sequence is “

01” and

to invert it when the logical configuration of said second sequence is “

10”

.

11. The device according to claim 9, further comprising a first additional element for detecting errors in the configuration of the bits of said second sequence by detecting a predetermined logical configuration.

12. The device according to claim 9, further comprising a second additional element for detecting an erroneous configuration of said slice after decoding, when the logical configuration of the bits of said second sequence indicates that said bit has been inverted during said encoding, said erroneous configuration appearing when the 3 bits of said slice are in the same logical state.