Variable level memory

• US 6,643,169 B2
• Filed: 09/18/2001
• Issued: 11/04/2003
• Est. Priority Date: 09/18/2001
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Intel Corporation
• Inventors: Fackenthal, Richard E., Rudelic, John C.
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US09/955,282
• Publication Number:
  US 20030053333A1
• Time in Patent Office: 777 Days
• Field of Search: 365/185.28, 365/185.03
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

There exists a tradeoff between the fidelity of data storage and the number of bits stored in a memory cell. The number of bits may be increased per cell when fidelity is less important. The number of bits per cell may be decreased when fidelity is more important. A memory, in some embodiments, may change between storage modes on a cell by cell basis.

Claims

1. A method comprising:

storing data at a first density in a first cell in a first memory array;

storing data at a second density in a second cell in the first memory array;

changing the number bits stored per cell on the fly.

2. The method of claim 1 wherein storing data at a second density in a second cell includes storing fewer bits per cell in one of said first or second cells.

3. The method of claim 1 including changing the number of bits stored per cell on the fly.

4. The method of claim 2 including storing data at levels which are spaced from one another in said cell in order to improve the read fidelity.

5. The method of claim 4 including storing data in a cell including a plurality of levels and filling less than all of said levels.

6. The method of claim 5 including storing data in regularly spaced levels within a cell while leaving intervening levels within the cell unoccupied by stored data.

7. An article comprising a medium storing instructions, that, if executed, enable a processor-based system to:

store data at a first density in a first cell in a first memory array;

store data at a second density in a second cell in said first memory array; and

change the number of bits stored per cell on the fly.

8. The article of claim 7 further storing instructions that enable the processor-based system to store fever bits per cell in one of said first or second cells.

9. The article of claim 8 further storing instructions that enable the processor-based system to store data at levels which are spaced from one another in said cell in order to improve the read fidelity.

10. The article of claim 9 further storing instructions that enable the processor-based system to store data in a cell including a plurality of levels and fill less than all of said levels.

11. The article of claim 10 further storing instructions that enable the processor-based system to store data in regularly spaced levels within a cell while leaving intervening levels within the cell unoccupied by stored data.

12. A memory comprising:

a memory array including a first and second cell; and

a controller coupled to said array to store data in said array at a first density in the first cell and to store data at a second density in the second cell wherein said controller changes the number of bits stored per cell on the fly.

13. The memory of claim 12 wherein said memory is a flash memory.

14. The memory of claim 13 wherein said memory is a multi-level cell memory.

15. The memory of claim 12 wherein said controller stores fewer bits per cell in one of said first or second cells.

16. The memory of claim 12 wherein said controller stores data at levels that are spaced from one another in said cell in order to improve the read fidelity.

17. The memory of claim 16 wherein said controller stores data in a cell including a plurality of levels and fills less than all of the levels.

18. The memory of claim 12 wherein said controller stores data in regularly spaced levels within a cell while leaving intervening levels within the cell unoccupied by stored data.

19. A method comprising:

storing data at a first density in a first cell in a first memory;

storing data at a second density in a second cell in the first memory; and

changing a number orbits stored per cell on the fly.

20. The method of claim 19 wherein storing data at a second density in a second cell includes storing fewer bits per cell in one of said first or second cells.

21. A method comprising:

storing data at a first density in a first cell in a first memory;

storing data at a second density in a second cell in the first memory, including storing fewer bits per cell in one of said first or second cells; and

storing data at levels which are spaced from one another in at least one of said first cell and said second cell in order to improve read fidelity.

22. The method of claim 21 including storing data in a cell including a plurality of levels and tilling less than all of said levels.

23. The method of claim 22 including storing data in regularly spaced levels within a cell while leaving intervening levels within the cell unoccupied by stored data.

24. An article comprising a medium storing instructions that enable a processor-based system to:

store data at a first density in a first cell in a first memory;

store data at a second density in a second cell in said first memory; and

store instructions that enable the processor-based system to change a number of bits stored per cell on the fly.

25. The article of claim 24 further storing instructions that enable the processor-based system to store fewer bits per cell in one of said first or second cells.

26. An article comprising a medium storing instructions that enable a processor-based system to:

store data at a first density in a first cell in a first memory;

store data at a, second density in a second cell in said first memory; and

store fewer bits per cell in one of said first or second cells; and

store data at levels which are spaced from one another in said cell in order to improve read fidelity.

27. The article of claim 26 further storing instructions that enable the processor-based system to store data in a cell including a plurality of levels and fill less than all of said levels.

28. The article of claim 27 further storing instructions that enable the processor-based system to store data in regularly spaced levels within a cell while leaving intervening levels within the cell unoccupied by stored data.

29. A memory comprising:

a memory array including a first and second cell; and

a controller coupled to said array to store data in said array at a first density in the first cell and to store data at a second density in the second cell, wherein said controller changes a number of bits stored per cell on the fly.

30. The memory of claim 29 wherein said controller stores data at levels that are spaced from one another in said cell in order to improve read fidelity.

31. The memory of claim 30 wherein said controller stores data in a cell including a plurality of levels and fills less than all of the levels.

32. The memory of claim 29 wherein said memory is a flash memory.

33. The memory of claim 32 wherein said memory is a multi-level cell memory.

34. The memory of claim 29 wherein said controller stores fewer bits per cell in one or said first or second cells.

35. A memory comprising:

a memory array including a first and second cell; and

a controller coupled to said array to store data in said array at a first density in the first cell and to store data at a second density in the second cell and to store data in regularly spaced levels within a cell while leaving intervening levels within the cell unoccupied by stored data.

36. The memory of claim 35 wherein said memory is a flash memory.

37. The memory of claim 36 wherein said memory is a multi-level cell memory.

38. The memory of claim 35 wherein said controller stores fewer bits per cell in one or said first or second cells.

39. A method comprising:

storing data at a first density in a first cell in a first memory array;

storing data at a second density in a second cell in the first memory array, so that fewer bits per cell are stored in one of said first and second cells;

storing data at levels which are spaced from one another in said cells.

40. The method of claim 39 including storing data in a cell including a plurality of levels filling less than all of the levels.

41. The method of claim 40 including storing data in regularly spaced levels within a cell while leaving intervening levels within the cell unoccupied by stored data.

42. An article comprising a medium storing instructions that, if executed, enable a processor-based system to:

store data at a first density in a first cell in a first memory array;

store data in a second density in a second cell in said first memory array; and

store data at levels that are spaced from one another in said cell.

43. The article of claim 42 further storing instructions that, if executed, enable the processor-based system to store data in a cell including a plurality of levels that fills less of all of said levels.

44. The article of claim 43 further storing instructions that, if executed, enable the processor-based system to store data in regularly spaced levels within a cell while leaving intervening levels within the cell unoccupied by stored data.

45. A memory comprising:

a memory array including a first and second cell; and

a controller coupled to said array to store data in said array at a first density in a first cell and to store data at a second density in a second cell, and to store data at levels that are spaced from one another in said cells.

46. The memory of claim 45 wherein said controller stores data in a cell including a plurality of levels that fills less than all of the levels.

47. The memory of claim 45 wherein said controller stores data in regularly spaced levels within a cell while leaving intervening levels within the cells unoccupied by stored data.

48. A method comprising:

storing data at a first density in a first cell in a first memory array;

storing data at a second density in a second cell in a first memory array; and

storing data in regularly spaced levels within a cell while leaving intervening levels within the cell unoccupied by stored data.

49. The method of claim 48 including storing data in a cell including a plurality of levels filling less than all said levels.

50. The method of claim 49 including changing the number of bits stored per cell on the fly.

51. An article comprising a medium storing instructions that, if executed, enable a processor-based system to:

store data at a first density in a first cell in a first memory array;

store data at a second density in a second cell in said first memory array; and

store data in regularly spaced levels within a cell while leaving intervening levels within the cell unoccupied by stored data.

52. The article of claim 51 further storing instructions that, if executed, enable a processor-based system to store data at levels which are spaced from one another in said cell in order to improve the read fidelity.

53. The article of claim 52 further storing instructions that, if executed, enable a processor-based system to change the number of bits stored per cell on the fly.

54. A memory comprising:

a memory array including a first and second cell; and

a controller coupled to said array to store data in said array at a first density in the first cell and to store data at a second density in the second cell and to store data in regularly spaced levels within a cell while leaving intervening levels within the cell unoccupied by stored data.

55. The memory of claim 54 wherein said controller stores data in a cell including a plurality of levels that fills less than all of the levels.

56. The memory of claim 55 wherein said controller changes the number of bits stored per cell on the fly.