Frequency detection circuit for clock recovery

• US 6,643,346 B1
• Filed: 02/23/1999
• Issued: 11/04/2003
• Est. Priority Date: 02/23/1999
• Status: Expired due to Term

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Rockwell Scientific Company, LLC (Teledyne Technologies Incorporated)
• Inventors: Pedrotti, Ken D., Price, Alistair J.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Yeh, Edith
• Application Number:
  US09/255,764
• Time in Patent Office: 1,715 Days
• Field of Search: 375/180, 375/375, 375/282, 375/374, 375/376, 331/11, 331/10, 331/2
• US Class Current: 375/375
• CPC Class Codes: G09G 5/008 Clock recovery
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/101 using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop H03L7/113, H03L7/187 take precedence
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A frequency detector is configured to provide reliable acquisition by a clock recovery and data regeneration circuit. A preferred frequency detector utilizes the output characteristics of a phase detector to determine a frequency difference between the recovered clock signal and the incoming data signal. The frequency detector then outputs a signal representing the frequency difference to a control device, preferably to a voltage-controlled oscillator (VCO). Upon receiving the frequency difference signal, the control device, preferably operating within a controlled-feedback loop, will begin to adjust the underlying clock frequency to approximate the incoming data frequency.

Claims

1. A clock recovery circuit having a phase locked loop for recovering an underlying clock signal from an input data stream, said clock recovery circuit comprising:

a phase detector for providing an output signal having characteristics representative of the frequency difference between the frequency of the underlying clock signal and the frequency of the input data stream;

a frequency detector, said frequency detector comprising a differentiator, a positive peak detector and a negative peak detector, said frequency detector responsive to said output signal of said phase detector, for providing an output signal corresponding to a magnitude of the frequency difference; and

an integrator, responsive to said output signal of said frequency detector, for providing a slowly varying bipolar voltage output signal proportional to the frequency difference.

2. The clock recovery circuit of claim 1, wherein said differentiator is responsive to said output signal of said phase detector, is for providing a differentiated output signal representative of the frequency difference, and

wherein said positive peak detector and said negative peak detector are coupled in parallel and determine the polarity of the differentiated output signal to indicate whether the frequency of the underlying clock signal is greater than or less than the frequency of the incoming data signal.

3. The clock recovery circuit of claim 2, wherein said phase locked loop comprises said phase detector, a loop filter and an oscillator control device, said integrator is coupled to said oscillator control device, and said slowly varying bipolar voltage output signal enables said oscillator control device to facilitate locking of the phase locked loop over an acquisition range exceeding the bandwidth of said loop filter in the phase locked loop.

4. The clock recovery circuit of claim 2, wherein said positive peak detector and said negative peak detector provide said corresponding output signal of the frequency detector to said integrator only if said differentiated output signal exceeds a threshold level.

5. The clock recovery circuit of claim 4, wherein said positive peak detector and said negative peak detector substantially reject low amplitude noise.

6. The clock recovery circuit of claim 2, wherein said frequency detector further comprises an inductive filter configured between said differentiator and said positive peak detector and said negative peak detector.

7. The clock recovery circuit of claim 6, wherein said inductive filter comprises a multipole filter.

8. The clock recovery circuit of claim 3, wherein said differentiator, said positive peak detector and said negative peak detector, and said integrator comprise a frequency detector loop for frequency alignment;

such that said frequency detector loop provides said slowly varying bipolar voltage output signal to said oscillator control device to enable said oscillator control device to control the clock recovery circuit to provide a recovered clock signal within at least the loop filter bandwidth of the frequency of the input data stream.

9. The clock recovery circuit of claim 8, wherein said phase locked loop operates to track the phase of the input data stream after said frequency detector loop has substantially enabled said oscillator control device to provide the recovered clock signal within at least the loop filter bandwidth of the frequency of the input data stream.

10. The clock recovery circuit of claim 9, wherein said positive peak detector and said negative peak detector provide said corresponding output signal of said frequency detector to said integrator only if said differentiated output signal exceeds a threshold level.

11. The clock recovery circuit of claim 10, wherein said positive peak detector and said negative peak detector substantially reject low amplitude noises.

12. The clock recovery circuit of claim 9, wherein said frequency detector loop further comprises an inductive filter configured between said differentiator and said positive peak detector and said negative peak detector.

13. The clock recovery circuit of claim 12, wherein said inductive filter comprises a multipole filter.

14. A frequency detector for providing a frequency difference signal for use with a clock extraction and data regeneration circuit, said frequency detector comprising:

a differentiator, responsive to an input signal representative of the frequency difference between the frequency of an underlying clock signal and the frequency of an incoming data signal, for providing a corresponding differentiated output signal; and

a pair of peak detectors responsive to the differentiated output signal, for providing an output voltage signal representative of said frequency difference to facilitate the frequency acquisition through a control device of the clock extraction and data regeneration circuit, wherein said pair of peak detectors comprises a positive peak detector and a negative peak detector for determining the polarity of pulses of said differentiated output signal.

15. The frequency detector of claim 14, wherein positive pulses in said differentiated output signal detected by the positive peak detector indicate to said control device that the frequency of the underlying clock signal is greater than the frequency of the incoming data signal, and negative pulses in said differentiated output signal detected by the negative peak detector indicate to said control device that the frequency of the underlying clock signal is less than the frequency of the incoming data signal.

16. The frequency detector of claim 15, wherein the magnitude of the output voltage signal of the pair of peak detectors indicates the amount of frequency difference.

17. The frequency detector of claim 14, wherein said output voltage signal representative of the frequency difference is provided only if the differentiated output signal exceeds a threshold level.

18. The frequency detector of claim 14, wherein said frequency detector further comprises an inductive filter.

19. The frequency detector of claim 18, wherein said inductive filter is configured between said differentiator and said pair of peak detectors.

20. The frequency detector of claim 19, wherein said inductive filter comprises a multipole filter.

21. The frequency detector of claim 15, further comprising a summing amplifier, responsive to said output voltage signal from said positive peak detector and said negative peak detector.

22. A clock extraction and data regeneration circuit for recovering an underlying clock signal from an incoming data signal, said clock extraction and data regeneration circuit comprising:

a first order phase locked loop comprising;

a phase detector for determining phase of the incoming data signal, and for providing an output signal having characteristics corresponding to the frequency difference between the frequency of said underlying clock signal and the frequency of said incoming data signal;

a loop filter having a defined bandwidth; and

a voltage-controlled oscillator for tracking the phase of the incoming data signal; and

a first order frequency detector loop comprising;

a differentiator, responsive to said output signal of said phase detector, for providing a differentiated output signal indicative of the frequency difference of the underlying clock signal and the incoming data signal;

a pair of peak detectors for determining the polarity of said output signal of said differentiator; and

an integrator, responsive to an output signal from said pair of peak detectors, for providing a slowly varying bipolar voltage to the voltage controlled oscillator;

wherein;

said first order frequency detector loop facilitates through said voltage-controlled oscillator locking of the first order phase locked loop over a frequency acquisition range exceeding the defined bandwidth of the loop filter.

23. The clock extraction and data regeneration circuit of claim 22, wherein said first order frequency detector loop provides said slowly varying bipolar voltage output signal to said voltage controlled oscillator to enable said voltage controlled oscillator to control the clock extraction and data regeneration circuit to provide a recovered clock signal with a frequency within at least the loop filter bandwidth of the frequency of the incoming data signal.

24. The clock extraction and data regeneration circuit of claim 23, wherein said first order phase locked loop tracks the phase of said incoming data signal after said first order frequency detector loop has substantially enabled said voltage controlled oscillator to provide said recovered clock signal.

25. The clock extraction and data regeneration circuit of claim 24, further comprising a second order phase locked loop for tracking of phase error of said underlying clock signal by said voltage-controlled oscillator, said second order phase locked loop configured in parallel with said first order phase locked loop, and said second order phase locked loop comprising an amplitude and offset control device for adjusting the offset of the output signal of said phase detector.

26. The clock extraction and data regeneration circuit of claim 23, wherein said pair of peak detectors comprises a positive peak detector and a negative peak detector for determining the polarity of pulses of said differentiated output signal.

27. A frequency detector for generating an output voltage representing the difference in frequency between a clock signal and an input signal, said frequency detector comprising:

a differentiator, responsive to said input signal, for generating an output signal corresponding to said difference in frequency; and

a pair of peak detectors, coupled in parallel, for generating said output voltage in response to said output signal of said differentiator wherein said pair of peak detectors comprises a positive peak detector and a negative peak detector for determining the polarity of pulses of said differentiated output signal.

28. The frequency detector of claim 27, wherein positive pulses in said differentiated output signal detected by said positive peak detector indicate that the frequency of said clock signal is greater than the frequency of said input signal, and negative pulses in said differentiated output signal detected by said negative peak detector indicate that the frequency of said clock signal is less than the frequency of said input signal.

29. The frequency detector of claim 28, wherein the magnitude of said output voltage signal of the pair of peak detectors corresponds to the amount of frequency difference between said clock signal and said input signal.

30. The frequency detector of claim 27, wherein said output voltage signal representative of the frequency difference is provided only if the differentiated output signal exceeds a threshold level.

31. The frequency detector of claim 30, wherein said frequency detector further comprises an inductive filter configured between said differentiator and said pair of peak detectors.

32. The frequency detector of claim 31, wherein said inductive filter comprises a multipole filter.

33. The frequency detector of claim 31, wherein said frequency detector further comprises an deductive filter configured prior to said differentiator for filtering an output signal phase detector, said inductive filter providing a filtered output signal to said differentiator.