CPU controlled memory controlling device for accessing operational information

• US 6,643,730 B2
• Filed: 06/13/2001
• Issued: 11/04/2003
• Est. Priority Date: 07/30/1998
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Hayashi, Tomohiro, Nagase, Takeshi, Gama, Shinkichi, Okumura, Yoshiki, Takamatsuya, Yoshihiro
• Primary Examiner(s): Verbrugge, Kevin
• Application Number:
  US09/879,118
• Publication Number:
  US 20020026555A1
• Time in Patent Office: 874 Days
• Field of Search: 711/5, 711/103, 711/170, 711/173
• US Class Current: 711/5
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence

Abstract

A memory controlling device is controlled by a CPU to enable information to be read from memory when the memory starts an operation. The memory is capable of retaining data during a power off state and the data is loaded when the memory starts an operation.

Claims

1. A memory device comprising:

a CPU;

a plurality of memories capable of retaining data thereof even when power is not supplied thereto; and

a controller which controls said plurality of memories in accordance with instructions from said CPU, wherein one of the plurality of memories stores information necessary for operation of the plurality of memories, and said CPU controls said controller to read the information from said one of the plurality of memories when said memory device starts an operation thereof and to store the information in a register, said information indicating a number and size of said plurality of memories and thereby allowing said CPU to enable a proper one of said plurality of memories when an access request is supplied from an exterior of said memory device.

2. The memory device as claimed in claim 1, wherein the information stored in said one or more memories is stored in a first one of said one or more memories.

3. The memory device as claimed in claim 1, wherein said CPU receives the information from an exterior of said memory device, and stores the information in said one or more memories.

4. The memory device as claimed in claim 1, wherein the information includes a code that is returned to a host device when the host device requests access to data that has been erased.

5. The memory device as claimed in claim 1, wherein the information includes identification information about a memory standard.

6. The memory device as claimed in claim 1, wherein the information includes information about whether specified bits of a specified register are valid or invalid.

7. The memory device as claimed in claim 1, wherein the information includes information about a method of generating an internal table.

8. The memory device as claimed in claim 1, wherein the information includes a time length that passes before said memory device enters a lower-power-consumption mode.