Method and apparatus for pre-fetching audio data
First Claim
Patent Images
1. An audio system comprising:
- a memory storing a sound sample;
an audio signal processor for processing the sound sample;
addressing circuitry for addressing the memory to read the sound sample therefrom, the addressing circuitry addressing the memory from a first address to a second address and then looping back one or more times to a third address between the first and second addresses; and
a pre-fetch storage area for storing data for a current address and for one or more following addresses to hide memory access latency during the looping back of the addressing circuitry to the third address, wherein the addressing circuitry comprises a starting address register, an ending address register and a current address register.
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Abstract
An audio system includes a memory storing audio data and an audio signal processor for processing the audio data. Addressing circuitry addresses the memory and a pre-fetch storage area stores data for a current address and for one or more following addresses to hide memory access latency during address changes of the addressing circuitry.
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Citations
33 Claims
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1. An audio system comprising:
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a memory storing a sound sample;
an audio signal processor for processing the sound sample;
addressing circuitry for addressing the memory to read the sound sample therefrom, the addressing circuitry addressing the memory from a first address to a second address and then looping back one or more times to a third address between the first and second addresses; and
a pre-fetch storage area for storing data for a current address and for one or more following addresses to hide memory access latency during the looping back of the addressing circuitry to the third address, wherein the addressing circuitry comprises a starting address register, an ending address register and a current address register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An audio system comprising:
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a memory storing a sound sample;
an audio signal processor for processing the sound sample;
addressing circuitry for addressing the memory to read the sound sample therefrom, the addressing circuitry addressing the memory from a first address to a second address and then looping back one or more times to a third address between the first and second addresses; and
a pre-fetch storage area for storing data for a current address and for one or more following addresses to hide memory access latency during the looping back of the addressing circuitry to the third address, wherein the addressing circuitry comprises a current address register which includes a bit for determining read/write access to the memory. - View Dependent Claims (14)
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15. An audio system comprising:
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a memory storing a sound sample;
an audio signal processor for processing the sound sample;
addressing circuitry for addressing the memory to read the sound sample therefrom, the addressing circuitry addressing the memory from a first address to a second address and then looping back one or more times to a third address between the first and second addresses; and
a pre-fetch storage area for storing data for a current address and for one or more following addresses to hide memory access latency during the looping back of the addressing circuitry to the third address, wherein the pre-fetch storage area is three data lines. - View Dependent Claims (16)
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17. A method of reading an audio sample from a memory for processing by an audio digital signal processor comprising:
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addressing the memory from a first address to a second address and then looping back one or more times to a third address between the first and second addresses to read the audio sample; and
storing data for a current address and for one or more following addresses in a pre-fetch storage area to hide memory access latency during the looping back to the third address, wherein the addressing comprises reading/writing from/to a starting address register, an ending address register and a current address register. - View Dependent Claims (18, 19, 20, 21, 22)
decoding data from the pre-fetch storage area.
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23. A video game machine comprising:
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a mass storage access device for accessing a mass storage device storing a video game program;
a video game program executing system for executing the video game program;
a memory for storing a sound sample for the video game program;
an audio digital signal processor for processing the sound sample;
addressing circuitry for addressing the memory to read the sound sample therefrom, the addressing circuitry addressing the memory from a starting address to an ending address and then looping back one or more times to a loop address between the starting and ending addresses, wherein the addressing circuitry comprises a starting address register, an ending address register and a current address register; and
a storage area for storing data for a current address and for one or more following addresses to hide memory access latency during the looping back of the addressing circuitry to the loop address. - View Dependent Claims (24, 25, 26, 27, 28)
a decoder for decoding data supplied thereto from the storage area.
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25. The video game machine according to claim 23, wherein the addressing circuitry is operable in a plurality of different addressing modes.
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26. The video game machine according to claim 23, wherein the addressing circuitry is selectively operable in a 4-bit, an 8-bit and a 16-bit addressing mode.
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27. The video game machine according to claim 23, wherein the storage area is a plurality of data lines.
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28. The video game machine according to claim 23, wherein the starting address register, the ending address register and the current address register are readable and writable by the audio digital signal processor.
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29. A method for a video game machine comprising a mass storage access device for accessing a mass storage device storing a video game program, a video game program executing system for executing the video game program, a memory for storing a sound sample for the video game, an audio digital signal processor for processing the sound sample, and addressing circuitry for addressing the memory to read the sound sample therefrom, wherein the addressing circuitry comprises a starting address register, an ending address register and a current address register, the method comprising:
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addressing the audio memory from a starting address specified in the starting address register to an ending address specified in the ending address register and then looping back one or more times to a loop address between the starting and ending addresses to read the sound sample; and
storing data for a current address and for one or more following addresses in a storage area to hide memory access latency during the looping back to the loop address. - View Dependent Claims (30, 31, 32)
decoding data from the storage area.
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33. A video game machine comprising:
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mass storage access means for accessing a mass storage device storing a video game program;
video game program executing means for executing the video game program;
memory for storing a sound sample for the video game program;
audio digital signal processing means for processing the sound sample;
addressing means for addressing the audio memory to read the sound sample therefrom, the addressing means addressing the audio memory from a starting address to an ending address and then looping back from the ending address one or more times to a loop address between the starting and ending addresses, wherein the addressing means comprises a starting address register, an ending address register and a current address register; and
storing means for storing data for a current address and for one or more following addresses to hide memory access latency during the looping back of the addressing means to the loop address.
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Specification