Method and apparatus for pre-fetching audio data

• US 6,643,744 B1
• Filed: 08/23/2000
• Issued: 11/04/2003
• Est. Priority Date: 08/23/2000
• Status: Expired due to Term

• Current Assignee: Nintendo Company Limited
• Original Assignee: Nintendo Company Limited
• Inventors: Cheng, Howard H.
• Primary Examiner(s): Sparks, Donald
• Assistant Examiner(s): Peugh, Brian R.
• Application Number:
  US09/643,984
• Time in Patent Office: 1,168 Days
• Field of Search: 711/212, 711/213, 711/217, 711/218, 711/137, 711/169, 711/1, 711/5, 711/220, 700/94, 712/210
• US Class Current: 711/137
• CPC Class Codes: A63F 13/10 Control of the course of the game, e.g. start, progess, end
• CPC Class Codes: A63F 13/45 Controlling the progress of the video game
• CPC Class Codes: A63F 13/54 involving acoustic signals, e.g. for simulating revolutions per minute [RPM] dependent engine sounds in a driving game or reverberation against a virtual wall
• CPC Class Codes: A63F 2300/6063 for sound processing
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G10L 19/00 Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis in musical instruments G10H

Abstract

An audio system includes a memory storing audio data and an audio signal processor for processing the audio data. Addressing circuitry addresses the memory and a pre-fetch storage area stores data for a current address and for one or more following addresses to hide memory access latency during address changes of the addressing circuitry.

Claims

1. An audio system comprising:

a memory storing a sound sample;

an audio signal processor for processing the sound sample;

addressing circuitry for addressing the memory to read the sound sample therefrom, the addressing circuitry addressing the memory from a first address to a second address and then looping back one or more times to a third address between the first and second addresses; and

a pre-fetch storage area for storing data for a current address and for one or more following addresses to hide memory access latency during the looping back of the addressing circuitry to the third address, wherein

the addressing circuitry comprises a starting address register, an ending address register and a current address register.

2. The audio system according to claim 1, wherein the addressing circuitry is operable in a plurality of different addressing modes for reading the sound sample from the memory.

3. The audio system according to claim 2, wherein one of the addressing modes is a 4-bit addressing mode.

4. The audio system according to claim 2, wherein one of the addressing modes is an 8-bit addressing mode.

5. The audio system according to claim 2, wherein one of the addressing modes is a 16-bit addressing mode.

6. The audio system according to claim 2, wherein the addressing circuitry is operable in one of a 4-bit, an 8-bit and a 16-bit addressing mode.

7. The audio system according to claim 1, wherein the starting address register, the ending address register and the current address register can be read/written by the audio digital signal processor.

8. The audio system according to claim 1, wherein the addressing circuitry further comprises address generating circuitry for generating addresses for addressing the memory based on the contents of the starting address register, the ending address register and the current address register.

9. The audio system according to claim 1, wherein the pre-fetch storage area operates as a FIFO.

10. The audio system according to claim 1, wherein the pre-fetch storage area stores pre-fetched data for the next two addresses after the current address.

11. The audio system according to claim 1, wherein the pre-fetch storage area comprises a plurality of data lines organized as a FIFO.

12. The audio system according to claim 1, further comprising a decoder for decoding data supplied thereto from the pre-fetch storage area.

13. An audio system comprising:

a memory storing a sound sample;

an audio signal processor for processing the sound sample;

addressing circuitry for addressing the memory to read the sound sample therefrom, the addressing circuitry addressing the memory from a first address to a second address and then looping back one or more times to a third address between the first and second addresses; and

a pre-fetch storage area for storing data for a current address and for one or more following addresses to hide memory access latency during the looping back of the addressing circuitry to the third address,

wherein the addressing circuitry comprises a current address register which includes a bit for determining read/write access to the memory.

14. The audio system according to claim 13, further comprising a decoder for decoding data supplied thereto from the pre-fetch storage area.

15. An audio system comprising:

a memory storing a sound sample;

an audio signal processor for processing the sound sample;

addressing circuitry for addressing the memory to read the sound sample therefrom, the addressing circuitry addressing the memory from a first address to a second address and then looping back one or more times to a third address between the first and second addresses; and

a pre-fetch storage area for storing data for a current address and for one or more following addresses to hide memory access latency during the looping back of the addressing circuitry to the third address,

wherein the pre-fetch storage area is three data lines.

16. The audio system according to claim 15, further comprising a decoder for decoding data supplied thereto from the pre-fetch storage area.

17. A method of reading an audio sample from a memory for processing by an audio digital signal processor comprising:

addressing the memory from a first address to a second address and then looping back one or more times to a third address between the first and second addresses to read the audio sample; and

storing data for a current address and for one or more following addresses in a pre-fetch storage area to hide memory access latency during the looping back to the third address, wherein

the addressing comprises reading/writing from/to a starting address register, an ending address register and a current address register.

18. The method according to claim 17, wherein the memory is addressed in one of a plurality of different addressing modes.

19. The method according to claim 17, wherein one of the addressing modes is a 4-bit addressing mode.

20. The method according to claim 17, wherein one of the addressing modes is an 8-bit addressing mode.

21. The method according to claim 17, wherein one of the addressing modes is a 16-bit addressing mode.

22. The method according to claim 17, further comprising:

decoding data from the pre-fetch storage area.

23. A video game machine comprising:

a mass storage access device for accessing a mass storage device storing a video game program;

a video game program executing system for executing the video game program;

a memory for storing a sound sample for the video game program;

an audio digital signal processor for processing the sound sample;

addressing circuitry for addressing the memory to read the sound sample therefrom, the addressing circuitry addressing the memory from a starting address to an ending address and then looping back one or more times to a loop address between the starting and ending addresses, wherein the addressing circuitry comprises a starting address register, an ending address register and a current address register; and

a storage area for storing data for a current address and for one or more following addresses to hide memory access latency during the looping back of the addressing circuitry to the loop address.

24. The video game machine according to claim 23, further comprising:

a decoder for decoding data supplied thereto from the storage area.

25. The video game machine according to claim 23, wherein the addressing circuitry is operable in a plurality of different addressing modes.

26. The video game machine according to claim 23, wherein the addressing circuitry is selectively operable in a 4-bit, an 8-bit and a 16-bit addressing mode.

27. The video game machine according to claim 23, wherein the storage area is a plurality of data lines.

28. The video game machine according to claim 23, wherein the starting address register, the ending address register and the current address register are readable and writable by the audio digital signal processor.

29. A method for a video game machine comprising a mass storage access device for accessing a mass storage device storing a video game program, a video game program executing system for executing the video game program, a memory for storing a sound sample for the video game, an audio digital signal processor for processing the sound sample, and addressing circuitry for addressing the memory to read the sound sample therefrom, wherein the addressing circuitry comprises a starting address register, an ending address register and a current address register, the method comprising:

addressing the audio memory from a starting address specified in the starting address register to an ending address specified in the ending address register and then looping back one or more times to a loop address between the starting and ending addresses to read the sound sample; and

storing data for a current address and for one or more following addresses in a storage area to hide memory access latency during the looping back to the loop address.

30. The method according to claim 29, wherein the memory is selectively addressed in one plurality of different addressing modes.

31. The method according to claim 29, wherein the memory is selectively addressed in one of a 4-bit, an 8-bit and a 16-bit addressing mode.

32. The method according to claim 29, further comprising:

decoding data from the storage area.

33. A video game machine comprising:

mass storage access means for accessing a mass storage device storing a video game program;

video game program executing means for executing the video game program;

memory for storing a sound sample for the video game program;

audio digital signal processing means for processing the sound sample;

addressing means for addressing the audio memory to read the sound sample therefrom, the addressing means addressing the audio memory from a starting address to an ending address and then looping back from the ending address one or more times to a loop address between the starting and ending addresses, wherein the addressing means comprises a starting address register, an ending address register and a current address register; and

storing means for storing data for a current address and for one or more following addresses to hide memory access latency during the looping back of the addressing means to the loop address.