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Transceiver with latency alignment circuitry

  • US 6,643,752 B1
  • Filed: 12/09/1999
  • Issued: 11/04/2003
  • Est. Priority Date: 12/09/1999
  • Status: Expired due to Term
First Claim
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1. A memory module configured to be coupled to a primary channel for receiving data and control signals from a controller, the memory module comprising:

  • a memory integrated circuit (IC);

    a secondary channel configured to transmit the data and control signals to the memory IC; and

    a transceiver coupled to the primary channel and the secondary channel, the transceiver electrically isolating the secondary channel from the primary channel, the transceiver being a low latency repeater to permit the data and the control signals from the controller to reach the memory (IC), wherein the transceiver is further configured such that a round trip latency of a data request from the controller to the memory IC is independent of a distance of the of memory IC from the controller.

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