Transceiver with latency alignment circuitry

• US 6,643,752 B1
• Filed: 12/09/1999
• Issued: 11/04/2003
• Est. Priority Date: 12/09/1999
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Johnson, Mark, Donnelly, Kevin, Tran, Chanh, Dillon, John B.
• Primary Examiner(s): Sparks, Donald
• Assistant Examiner(s): CHACE, CHRISTIAN
• Application Number:
  US09/458,582
• Time in Patent Office: 1,426 Days
• Field of Search: 365/189.05, 365/189.07, 365/189.08, 365/191, 365/233, 709/208, 709/217, 709/232, 709/248, 709/400, 710/6, 710/25, 710/29, 710/36, 710/45, 710/58, 710/60, 710/61, 710/106, 711/154, 711/167, 713/400, 713/500, 713/600
• US Class Current: 711/167
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/405 where the bridge performs a synchronising function
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

A transceiver system is described. A secondary memory module is coupled to a primary channel for receiving data and signals from a controller. The secondary memory module comprises a memory and a secondary channel for transmitting the data and control signals to the memory. The secondary memory module further comprises a transceiver coupled to the primary channel and the secondary channel. The transceiver is designed to electrically isolate the secondary channel from the primary channel. The transceiver is a low latency repeater to permit the data and the control signals from the controller to reach the memory, such that a latency of a data request from the controller is independent of a distance of the transceiver from the controller.

Claims

1. A memory module configured to be coupled to a primary channel for receiving data and control signals from a controller, the memory module comprising:

a memory integrated circuit (IC);

a secondary channel configured to transmit the data and control signals to the memory IC; and

a transceiver coupled to the primary channel and the secondary channel, the transceiver electrically isolating the secondary channel from the primary channel, the transceiver being a low latency repeater to permit the data and the control signals from the controller to reach the memory (IC), wherein the transceiver is further configured such that a round trip latency of a data request from the controller to the memory IC is independent of a distance of the of memory IC from the controller.

2. The memory module of claim 1, wherein the transceiver further comprises:

a slave interface configured to receive the data and the signals on the primary channel synchronized to a first set of clock signals from the controller; and

a master interface configured to send data and signals on the secondary channel synchronized to a second set of clock signals to memories coupled to the secondary channel, such that the second set of clock signals is synchronized to a clock signal from the controller, making transactions from the secondary channel to the primary channel synchronous.

3. The memory module of claim 2, wherein the first set of clock signals comprises a clock-to-master (CTM) signal and a clock-from-master (CFM) signal, and

the second set of clock signals is synchronized to the CTM signal.

4. The memory module of claim 1, wherein transmitters in the transceiver are synchronized to align I/O switching noise.

5. The memory module of claim 1, wherein the transceiver comprises:

a primary receiver configured to receive the data and the signals from the primary channel;

a primary transmitter configured to transmit the data and the signals to the primary channel;

a secondary transmitter configured to transmit the data and the signals to the secondary channel;

a secondary receiver configured to receive the data and the signals from the secondary channel; and

a re-timer located between the primary receiver and the secondary transmitter to re-time the data and the signals from a clock signal on the primary channel to a clock signal on the secondary channel.

6. The memory module of claim 5, wherein the clock signal on the secondary channel is synchronized to the clock signal on the primary channel, and wherein the transceiver is configured to retransmit data from the secondary channel to the primary channel without re-timing the retransmitted data.

7. The memory module of claim 5, wherein the low latency repeater is a bi-directional repeater, and the repeater includes latch-up prevention logic to prevent feedback latch-up between the primary channel and the secondary channel, the latch-up prevention logic preventing re-transmittal of information received by the primary receiver from the primary channel by the primary transmitter back onto the primary channel.

8. The memory module of claim 1, wherein the latch-up prevention logic includes disable logic configured to block data transmission from the primary channel to the secondary channel, while permitting transmission from the secondary channel to the primary channel.

9. The memory module of claim 1, wherein the transceiver is configured to be positioned with respect to the controller such that a time of flight of the data and control signals from the controller to the transceiver over the primary channel is less than one half of a predefined clock cycle of a clock signal with which transmission of the data over the primary channel is synchronized.

10. A memory system comprising:

a memory master coupled to a memory channel;

a transceiver coupled to the memory channel, the transceiver configured to receive data from the memory master with a clock-from-master (CFM) timing, the transceiver further configured to re-time the data from the memory master and to transmit the data to memory integrated circuit (IC) devices coupled to the transceiver with a clock-from-transceiver (CFT) timing, and the transceiver also configured to receive data from the memory IC devices with a clock-to-transceiver (CTT) timing and to transmit, the data to the memory master with a clock-to-master (CTM) timing;

wherein the CFM and CTM are clock signals traveling over the memory channel in opposite directions, the CTT and CFT and clock signals traveling over a secondary channel in opposite directions, and the CTT and the CFT are synchronized to the CTM, such that data transmitted from the memory IC devices to the memory master is not re-timed by the transceiver.

11. The memory system of claim 10, wherein the transceiver is further configured such that a round trip latency from the memory master to the memory IC is independent of a distance of the memory IC devices from the, memory master.

12. A transceiver comprising:

a slave interface coupled to a primary channel for receiving data from and transmitting data to a memory master using clock-from master (CFM) and clock-to-master (CTM) signals;

a master interface coupled to a secondary channel for receiving data from and transmitting data to a memory integrated circuit (IC) using clock-to-transceiver (CTT) and clock-from-transceiver (CFT) signals; and

transceiver circuitry coupled to the slave interface and master interface for retransmitting using the CTM signal the data received at the slave interface with the CTT signal;

the transceiver circuitry including a re-timer for re-timing data received with the CFM signal from the primary channel to retransmit the data with the CFT signal on the secondary channel;

wherein the transceiver circuitry is configured such that no re-timing is performed by the transceiver circuitry when retransmitting to the primary channel, using the CTM signal, the data received from the secondary channel, using the CTT signal.

13. The transceiver of claim 12, the transceiver circuitry comprising:

a primary receiver configured to receive the data and the signals from the primary channel;

a primary transmitter configured to transmit the data and the signals to the primary channel;

a secondary transmitter configured to transmit the data and the signals to the secondary channel;

a secondary receiver configured to receive the data and the signals from the secondary channel; and

the re-timer located between the primary receiver and the secondary transmitter to re-timing the data and the signals from a clock signal on the secondary channel to a clock signal on the primary channel.

14. The transceiver of claim 12, further comprising:

isolation logic to isolate the transceiver from the primary channel to prevent transmission of data on the primary channel to the secondary channel.

15. The transceiver of claim 12, further comprising:

latch-up prevention logic to prevent feedback of data between the primary channel and the secondary channel.

16. The transceiver of claim 12, wherein the transceiver is further configured such that a round trip latency from the memory master to the memory IC is independent of a distance of the memory IC from the memory master.

17. A method of extending a memory channel comprising:

receiving data from and transmitting data to a memory master on a primary channel;

receiving data from and transmitting data to a memory integrated circuit (IC) on a secondary channel;

re-timing data received from the primary channel to retransmit the data on the secondary channel, such that the data on the primary channel is clocked to a first primary clock while the data on the secondary channel is clocked to a first secondary clock;

retransmitting data received from the secondary channel using a second secondary clock onto the primary channel using a second primary clock;

wherein the first and second primary clocks are transmitted in opposite directions on the primary channel, and the first and second secondary clocks are transmitted in opposite directions on the secondary channel; and

synchronizing a the second secondary clock on the secondary channel to the second primary clock on the primary channel such that data transmitted from the secondary channel to the primary channel is not re-timed.

18. The method of claim 17, further comprising:

blocking data received on the secondary channel from the primary channel from being retransmitted to the primary channel to prevent latch-up.

19. The method of claim 18, wherein the step of blocking comprises:

disabling a transmitter when a data is received on the secondary channel.

20. The method of claim 18, further comprising:

isolating the transceiver to prevent transmission of data from the primary channel to the secondary channel.

21. The method of claim 17, wherein the clocks that are synchronized are a clock-to-master (CTM) on the primary channel and a clock-to-transceiver (CTT) on the secondary channel.

22. The method of claim 17, wherein a round trip latency from the memory master to the memory IC is independent of a distance of the memory IC from the memory master.

23. A clocking scheme for extending a memory channel from a memory master, the clocking scheme comprising:

a clock-from-master (CFM) for clocking data sent by the memory master to a transceiver;

a clock-to-master (CTM) for clocking data sent to the memory master by the transceiver, the CFM and CTM coupled together in the memory master;

a clock-to-transceiver (CTT) for clocking data received by the transceiver from a memory integrated circuit (IC) device;

a clock-from-transceiver (CFT) for clocking data sent by the transceiver to the memory IC device;

a re-timer for re-timing data received with the CFM from the memory master, such that the data is sent to the memory device with the CFT; and

a synchronizer for synchronizing the CTM and the CTT, such that data sent from the memory device to the memory master is not re-timed when that data is received from the memory device and retransmitted by the transceiver to the memory master.

24. The clocking scheme of claim 23, wherein a round trip latency from the memory master to the memory IC is independent of a distance of the memory IC from the memory master.

25. A method of extending a memory channel by coupling a transceiver between a master device and a memory device, the method comprising:

transmitting data from the master device on a primary channel to the memory device on a secondary channel through the transceiver, the data transfer having a latency of (2.5×

t_CYCLE)−

t_TR′

, where t_TR depends on a distance of the transceiver from the master device;

transmitting data from the memory device on a secondary channel to the master device on a primary channel, the data transfer having a latency of 1.5×

t_cycle+t_TR′

,

such that a latency of a round trip of the master device requesting data and the memory device supplying the data is (1.5×

t_cycle+t_TR)+(2.5×

t_cycle−

t_TR)=4×

t_CYCLE′

thus the latency is independent of the distance of the transceiver from the master device.