Programmable processor with group floating point operations

• US 6,643,765 B1
• Filed: 03/24/2000
• Issued: 11/04/2003
• Est. Priority Date: 08/16/1995
• Status: Expired due to Fees

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Moussouris, John, Hansen, Craig
• Primary Examiner(s): Bella, Matthew C.
• Assistant Examiner(s): Monestime, Mackly
• Application Number:
  US09/534,745
• Time in Patent Office: 1,320 Days
• Field of Search: 712/32, 712/28, 712/34, 712/208, 712/210
• US Class Current: 712/32
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/323 : for indirect branch instructions
• CPC Class Codes: G06F 9/3816 : Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/3824 : Operand accessing
• CPC Class Codes: G06F 9/383 : Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 : Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3873 : Variable length pipelines, e.g. elastic pipeline
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

A programmable processor that comprises a general purpose processor architecture, capable of operation independent of another host processor, having a virtual memory addressing unit, an instruction path and a data path; an external interface; a cache operable to retain data communicated between the external interface and the data path; at least one register file configurable to receive and store data from the data path and to communicate the stored data to the data path; and a multi-precision execution unit coupled to the data path. The multi-precision execution unit is configurable to dynamically partition data received from the data path to account for an elemental width of the data and is capable of performing group floating-point operations on multiple operands in partitioned fields of operand registers and returning catenated results. In other embodiments the multi-precision execution unit is additionally configurable to execute group integer and/or group data handling operations.

Claims

1. A programmable media processor comprising:

a general purpose processor architecture, capable of operation independent of another host processor, having a virtual memory addressing unit, an instruction path and a data path;

an external interface operable to receive data from an external source and communicate the received data over the data path;

a cache operable to retain data communicated between the external interface and the data path;

at least one register file configurable to receive and store data from the data path and to communicate the stored data to the data path; and

a multi-precision execution unit coupled to the data path, the multi-precision execution unit configurable to dynamically partition data received from the data path to account for an elemental width of the data wherein the elemental width of the data is equal to or narrower than the data path, the multi-precision execution unit being capable of performing group floating-point operations on multiple operands in partitioned fields of operand registers and returning catenated results.

2. The media processor of claim 1 wherein the multi-precision execution unit is capable of performing group add, group subtract and group multiply arithmetic operations on catenated floating-point data and, for each such group operation, returning catenated results of the operation to a register.

3. The media processor of claim 2 wherein at least some of the group add, group subtract and group multiply arithmetic operations perform arithmetic operations on floating-point data stored in first and second operand registers and return the catenated result to a result register.

4. The media processor of claim 3 wherein the result register is a different register than either the first or second operand registers.

5. The media processor of claim 1 wherein the multi-precision execution unit is capable of executing a first plurality of group floating-point operations on floating-point data of a first precision and a second plurality of group floating-point operations on floating-point data of a second precision that is a higher precision than the first precision and wherein a number of data elements stored in partitioned fields of the operand registers for the first and second plurality of group floating-point operations is inversely related to the precision of the data elements.

6. The media processor of claim 1 wherein the multi-precision execution unit is capable of executing group floating point operations that operate on 32-bit data elements and group floating-point operations that operate on 64-bit data elements and wherein a number of data elements stored in partitioned fields of operand registers used for the operations that operate on 32-bit data elements is twice as many as a number of data elements stored in partitioned fields of operand registers used for the operations that operate on 64-bit data elements.

7. The media processor of claim 1 wherein, when performing at least some of the group floating-point operations, the multi-precision execution unit operates on partitioned fields of operand registers in parallel and returns the catenated results to a register.

8. The media processor of claim 1 wherein the multi-precision execution unit is capable of executing a plurality of group floating-point operations on floating-point data of a first precision and a plurality of group floating-point operations on floating-point data of a second precision that is a higher precision than the first precision and wherein, when performing at least one of the group floating-point operations on floating-point data of the first precision, the multi-precision execution unit operates on at least two partitioned operands in parallel.

9. The media processor of claim 1 wherein the multi-precision execution unit is capable of performing group floating-point operations on catenated data having a total aggregate width of 128 bits.

10. The media processor of claim 1 wherein the multi-precision execution unit is capable of performing group floating-point operations on floating-point data of more than one precision.

11. The media processor of claim 1 wherein the multi-precision execution unit is capable of performing group integer operations on multiple operands in partitioned fields of operand registers and returning catenated results to a register.

12. The media processor of claim 11 wherein the multi-precision execution unit is capable of performing group add, group subtract and group multiply arithmetic operations on catenated integer data and, for each such group operation, returning catenated results of the operation to a register.

13. The media processor of claim 12 wherein at least some of the group add, group subtract and group multiply arithmetic operations perform arithmetic operations on integer data stored in first and second operand registers and return the catenated result to a result register.

14. The media processor of claim 11 wherein the multi-precision execution unit is capable of executing a first plurality of group integer operations on integer data of a first precision and a second plurality of group integer operations on integer data of a second precision that is a higher precision than the first precision and wherein a number of data elements stored in partitioned fields of the operand registers for the first and second plurality of group integer operations is inversely related to the precision of the data elements.

15. The media processor of claim 11 wherein, when performing at least some of the group integer operations, the multi-precision execution unit operates on partitioned fields of operand registers in parallel and returns the catenated results to a register.

16. The media processor of claim 11 wherein the multi-precision execution unit is capable of executing a plurality of group integer operations on integer data of a first precision and a plurality of group integer operations on integer data of a second precision that is a higher precision than the first precision and wherein, when performing at least one of the group integer operations on integer data of the first precision, the multi-precision execution unit operates on at least two partitioned operands in parallel.

17. The media processor of claim 1 wherein the multi-precision execution unit is capable of performing one or more group data handling operations that operate on multiple operands in partitioned fields of one or more operand registers and returning catenated results to a register.

18. The media processor of claim 17 wherein the one or more group data handling operations comprises a first group operation that converts a plurality of n-bit data elements in a first operand register and a plurality of n-bit data elements in a second operand register into a plurality of n/2-bit data elements in a result register.

19. The media processor of claim 18 wherein the first group operation shifts each of the plurality of n/2-bit data elements by a specified number of bits during the conversion.

20. The media processor of claim 17 wherein the one or more group data handling operations comprises a second group operation that interleaves a plurality of data elements selected from a first operand register with a plurality of data elements selected from a second operand register and catenates the data elements into a result register.

21. The media processor of claim 17 wherein the one or more data handling operations comprises a group shift left operation that shifts bits of individual data elements catenated in an operand register to the left and clears empty low order bits of the individual data elements to zero.

22. The media processor of claim 17 wherein the one or more data handling operations comprises a group shift right operation that shifts bits of individual data elements catenated in an operand register to the right and fills empty high order bits of the individual data elements with a value equal to a value stored in a sign bit of the individual data element.

23. The media processor of claim 17 wherein the one or more data handling operations comprises a group shift right operation that shifts bits of individual data elements catenated in an operand register to the right and clears empty high order bits of the individual data elements to zero.

24. The media processor of claim 17 wherein the multi-precision execution unit is capable of executing a first plurality of group data handling operations on data of a first precision and a second plurality of group data handling operations on data of a second precision that is a higher precision than the first precision and wherein a number of data elements stored in partitioned fields of the operand registers for the first and second plurality of group data handling operations is inversely related to the precision of the data elements.

25. The media processor of claim 17 wherein, when performing at least some of the group data handling operations, the multi-precision execution unit operates on partitioned fields of operand registers in parallel and returns the catenated results to a register.

26. The media processor of claim 17 wherein the multi-precision execution unit is capable of executing a plurality of group data handling operations on data of a first precision and a plurality of data handling operations on data of a second precision that is a higher precision than the first precision and wherein, when performing at least one of the group data handling operations on data of the first precision, the multi-precision execution unit operates on at least two partitioned operands in parallel.

27. The media processor of claim 1 wherein the multi-precision execution unit comprises a plurality of functional units.

28. The media processor of claim 1 wherein the at least one register file comprises a plurality of registers that can be used to store operands and results for the group floating-point operations.

29. The media processor of claim 1 wherein the multi-precision execution unit returns the catenated results to a register.

30. The media processor of claim 1 wherein the at least one register file comprises a plurality of general purpose registers that can be used as operand and result registers for group floating-point operations.