Virtual tree-based netlist model and method of delay estimation for an integrated circuit design

• US 6,643,832 B1
• Filed: 09/26/2001
• Issued: 11/04/2003
• Est. Priority Date: 09/29/2000
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Grinchuk, Mikhail I., Raspopovic, Pedja, Ray, Partha P. Data
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): THOMPSON, ANNETTE M
• Application Number:
  US09/964,011
• Time in Patent Office: 769 Days
• Field of Search: 716/6, 716/4, 703/15
• US Class Current: 716/108
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A pre-placement delay model for a logical function block of an integrated circuit design includes a fan-in count variable, a fan-out count variable and a delay variable. The fan-in count variable has a value indicative of a number of inputs to the logical function block. The fan-out count variable has a value indicative of the number of inputs of other logical function blocks that are driven by an output of the logical function block. The delay variable has a value that is a function of the binary logarithm of the fan-in count variable and the binary logarithm of the fan-out count variable.

Claims

1. A pre-placement delay model for a logical function block of an integrated circuit design, wherein the integrated circuit comprises a plurality of different types of the logical function block, the model comprising:

a fan-in count variable, having a value indicative of a number of inputs to the logical function block;

a fan-out count variable, having a value indicative of a number of inputs of other logical function blocks in the integrated circuit design that are driven by an output of the logical function block; and

a delay variable, which has a value that is a function of a sum of a first delay coefficient multiplied by a binary logarithm of the fan-in count variable and a second delay coefficient multiplied by a binary logarithm of the fan-out count variable, wherein the first delay coefficient comprises a first value for each of the plurality of types of the logical function block having only non-linear logical function gates and a second value for each of the types having a linear logical function gate.

2. The pre-placement delay model of claim 1 wherein the second delay coefficient has the same value for all of the different types of the logical function block.

3. The pre-placement delay model of claim 1 wherein the integrated circuit design is capable of being fabricated in a plurality of different semiconductor technologies and wherein:

the pre-placement delay model is generic to the plurality of different semiconductor technologies such that the first and second delay coefficients are the same for each of the plurality of different semiconductor technologies.

4. A method of modeling delay through a logical function block within an integrated circuit design prior to placement and routing, the method comprising:

(a) identifying a fan-in count indicative of a number of inputs to the logical function block;

(b) identifying a fan-out count indicative of a number of inputs to other logical function blocks in the integrated circuit design that are driven by an output of the logical function block;

(c) producing a propagation delay estimate for the logical function block as a function of the fan-in count and the fan-out count;

(d) identifying a plurality of Boolean functions;

(e) for each of the Boolean functions, identifying a plurality of different circuit configurations that implement that Boolean function with a plurality of cells selected from a particular semiconductor technology library;

(f) for each of the circuit configurations, producing a delay estimate as a function of load based on delay information provided with the technology library for the plurality of cells; and

(g) for each of the Boolean functions, selecting a minimum one of the delay estimates produced for that Boolean function in (e).

5. The method of claim 4 wherein (c) comprises:

(c)(1) multiplying a binary logarithm of the fan-in count by a first delay coefficient to produce a first product;

(c)(2) multiplying a binary logarithm of the fan-out count by a second delay coefficient to produce a second product; and

(c)(3) summing the first and second products to produce the delay estimate.

6. The method of claim 5 wherein the delay estimate produced in (c) is produced as a function of only the binary logarithms of the fan-in and fan-out counts and the first and second delay coefficients.

7. The method of claim 5 and further comprising:

(h) deriving the first and second delay coefficients based on the minimum delay estimates selected in (g).

9. The method of claim 7 and further comprising:

(i) performing (e) through (g) for a plurality of different semiconductor technology libraries; and

(j) deriving the first and second delay coefficients based on the minimum delay estimates selected in (g) for the plurality of different semiconductor technologies.

10. The method of claim 4 wherein (c) is performed prior to mapping the logical function block into cells of a specific cell technology library.

8. The method of claim wherein 7 comprises deriving the first and second delay coefficients based on a best-fit analysis of the minimum delay estimates as a function of load selected in (g) for the plurality of Boolean functions.

11. A generic semiconductor cell library which, for each cell in the library, comprises:

a functional model; and

propagation delay model means for modeling propagation delay through the cell as a function of only two design variables, a fan-in count variable and a fan-out count variable, prior to mapping the cell into at least one cell of a specific cell technology library, wherein the fan-in count variable indicates a number of inputs to the cell and the fan-out count variable indicates a number of inputs of other cells that are driven by an output of that cell.

12. The generic semiconductor cell library of claim 11 wherein the propagation delay model means comprises:

means for producing a propagation delay estimate for the cell as a function of a binary logarithm of the fan-in count variable and a binary logarithm of the fan-out count variable.

13. The generic semiconductor cell library of claim 12 wherein the propagation delay model means comprises:

means for multiplying the binary logarithm of the fan-in count variable by a first delay coefficient to produce a first product;

means for multiplying the binary logarithm of the fan-out count variable by a second delay coefficient to produce a second product; and

means for summing the first and second products to produce a propagation delay estimate.

14. A pre-placement delay model for a logical function block of an integrated circuit design, which is capable of being fabricated in a plurality of different semiconductor technologies, the model comprising:

a fan-in count variable, having a value indicative of a number of inputs to the logical function block;

a fan-out count variable, having a value indicative of a number of inputs of other logical function blocks in the integrated circuit design that are driven by an output of the logical function block; and

a delay variable, which has a value that is a function of a first delay coefficient multiplied by a binary logarithm of the fan-in count variable and a second delay coefficient multiplied by a binary logarithm of the fan-out count variable, wherein the pre-placement delay model is generic to the plurality of different semiconductor technologies such that the first and second delay coefficients are the same for each of the plurality of different semiconductor technologies.

15. A method of modeling delay through a logical function block within an integrated circuit design prior to placement and routing, the method comprising:

(a) identifying a fan-in count indicative of a number of inputs to the logical function block;

(b) identifying a fan-out count indicative of a number of inputs to other logical function blocks in the integrated circuit design that are driven by an output of the logical function block; and

(c) producing a propagation delay estimate for the logical function block as a function of a binary logarithm of the fan-in count and a binary logarithm of the fan-out count, prior to mapping the logical function block into cells of a specific cell technology library.