Method of and apparatus for designing layout of analog cells, and computer product

• US 6,643,834 B2
• Filed: 02/22/2002
• Issued: 11/04/2003
• Est. Priority Date: 09/14/2001
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubishi Electric System (Mitsubishi Electric Corporation)
• Inventors: Satoh, Takao, Koyama, Takashi, Senoh, Takeshi
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Lee, Granvill D.
• Application Number:
  US10/080,044
• Publication Number:
  US 20030056186A1
• Time in Patent Office: 620 Days
• Field of Search: 716/10, 716/1, 716/5, 716/9, 716/11, 716/12-14
• US Class Current: 716/139
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

Data corresponding to an analog circuit diagram is generated and stored. Circuit connection information is extracted based on the analog circuit diagram data and stored. Devices to be paired are predicted and extracted based on the circuit connection information. The devices added as design constraints to the circuit connection information, and the result of addition is stored. Layout cells are placed on the basis of the circuit connection information including the design constraints. Routing of the layout cells is conducted.

Claims

1. An analog cell layout designing apparatus comprising:

a circuit diagram generating unit which generates an analog circuit diagram;

a circuit diagram storing unit which stores circuit diagram data corresponding to the analog circuit diagram generated by said circuit diagram generating unit;

a circuit connection information extracting unit which extracts circuit connection information from the analog circuit diagram data stored in said circuit diagram storing unit;

a first circuit connection information storing unit which stores circuit connection information extracted by said circuit connection information extracting unit;

a design constraint predicting and extracting unit which predicts and extracts devices to be paired from the circuit connection information stored in said first circuit connection information storing unit and adding the devices extracted as design constraints to the circuit connection information;

a second circuit connection information storing unit which stores the circuit connection information to which the design constraints are added by said design constraint predicting and extracting unit;

an automatic placing unit which places layout cells selected based on the circuit connection information including the design constraints, stored in said second circuit connection information storing unit in accordance with a process design rule; and

an automatic routing unit which conducts routing of the layout cells placed by said automatic placing unit in accordance with the process design rule.

2. The analog cell layout designing apparatus according to claim 1, wherein said design constraints predicting and extracting unit comprises:

a node name giving unit which gives a node name to a power supply line and a ground line in the circuit connection information stored in said first circuit connection information storing unit;

a circuit connection information tree generating unit which generates a circuit connection information tree using the power supply line to which the node name is given as a start point and indicative of a connection relation of P-type transistor devices and a connection relation of resistive elements, and generates a circuit connection information tree using the ground line to which the node name is given as a start point and indicative of a connection relation of N-type transistor devices and a connection relation of resistive elements;

a grouping unit which groups devices of the same kind at the same level in each of the circuit connection information trees generated;

a group dividing unit which divides a group by selecting devices connected to the same line, other than the power supply line, or selecting devices connected to the same line, other than the ground line, from the devices in each of groups formed by said grouping unit;

a group coupling unit which couples groups sharing a device in the groups formed by said group dividing unit;

a design constraint adding unit which adds the groups formed by said group dividing unit, as pairing constraints, to the circuit connection information; and

an editing unit which edits the device pairing constraints added by said design constraint adding unit and writes the device pairing constraints after editing into said second circuit connection information storing unit.

3. The analog cell layout designing apparatus according to claim 2, wherein said design constraint predicting and extracting unit further comprises a circuit connection information rewriting unit which rewrites circuit connection information of each of the resistive elements, other than the resistive element having the lowest resistance, to information of serial connection of the resistive elements, each having the lowest resistance in a group of the resistive elements in the groups coupled by said group coupling unit, wherein said design constraint adding unit adds the device pairing constraint to the circuit connection information, including the circuit connection information rewritten by said circuit connection information rewriting unit.

4. The analog cell layout designing apparatus according to claim 2, wherein

said design constraint predicting and extracting unit further comprises a circuit connection information rewriting unit which rewrites circuit connection information of each of bipolar transistor devices, other than a bipolar transistor device having the smallest emitter size in a group of bipolar transistor devices in the groups formed by said group coupling unit, to information of parallel connection of the bipolar transistor devices each having the smallest emitter size, and

said design constraint adding unit adds the device pairing constraint to the circuit connection information, including the circuit connection information rewritten by said circuit connection information rewriting unit.

5. The analog cell layout designing apparatus according to claim 2, wherein said design constraint predicting and extracting unit further comprises a circuit connection information rewriting unit, and said circuit connection information rewriting unit performs at least one of,

rewriting of circuit connection information of each of MOS transistors, other than an MOS transistor device having the smallest gate width, to information of parallel connection of MOS transistor devices, each having the smallest gate width, when gate lengths of the MOS transistor devices are equal to each other, in a group of the MOS transistor devices in the groups formed by said group coupling unit;

and

rewriting of circuit connection information of each of the MOS transistors, other than the MOS transistor device having the smallest gate length, to information of serial connection of MOS transistor devices each having the smallest gate length when gate widths of the MOS transistor devices are equal to each other, wherein said design constraint adding unit adds said device pairing constraint to the circuit connection information, including the circuit connection information rewritten by said circuit connection information rewriting unit.

6. The analog cell layout designing apparatus according to claim 1, wherein said design constraint predicting and extracting unit comprises:

a node name giving unit which gives a node name to a power supply line and a ground line in the circuit connection information stored in said first circuit connection information storing unit;

a circuit connection information tree generating unit which generates a circuit connection information tree using the power supply line to which the node name is given as a start point and indicative of a connection relation of P-type transistor devices and a connection relation of resistive elements, and generates a circuit connection information tree using the ground line to which the node name is given as a start point and indicative of a connection relation of N-type transistor devices and a connection relation of resistive elements;

a grouping unit which groups devices of the same kind at the same level in each of said circuit connection information trees generated;

a group dividing unit which divides a group by selecting devices connected to the same line, other than the power supply line, or selecting devices connected to the same line, other than the ground line, from the devices in each of groups formed by said grouping unit;

a branch device grouping unit for, when a branch extending from the power supply line to the ground line and a branch extending from the ground line to the power supply line exist in the circuit connection information trees generated, grouping all devices of the same kind existing in each of the branches;

a group coupling unit which couples groups sharing a device in groups formed by said group dividing unit and groups formed by said branch device grouping unit;

a design constraint adding unit which adds the groups formed by said group dividing unit and the groups formed by said branch device grouping unit, as pairing constraints, to said circuit connection information; and

an editing unit which edits the device pairing constraint added by said design constraint adding unit and writes the device pairing constraints after editing into said second circuit connection information storing unit.

7. The analog cell layout designing apparatus according to claim 6, wherein said design constraint predicting and extracting unit further comprises a circuit connection information rewriting unit which rewrites circuit connection information of each of the resistive elements, other than the resistive element having the lowest resistance, to information of serial connection of the resistive elements, each having the lowest resistance in a group of the resistive elements in the groups coupled by said group coupling unit, wherein said design constraint adding unit adds the device pairing constraint to the circuit connection information, including the circuit connection information rewritten by said circuit connection information rewriting unit.

8. The analog cell layout designing apparatus according to claim 6, wherein

said design constraint predicting and extracting unit further comprises a circuit connection information rewriting unit which rewrites circuit connection information of each of bipolar transistor devices, other than a bipolar transistor device having the smallest emitter size in a group of bipolar transistor devices in the groups formed by said group coupling unit, to information of parallel connection of the bipolar transistor devices each having the smallest emitter size, and

said design constraint adding unit adds the device pairing constraint to the circuit connection information, including the circuit connection information rewritten by said circuit connection information rewriting unit.

9. The analog cell layout designing apparatus according to claim 6, wherein said design constraint predicting and extracting unit further comprises a circuit connection information rewriting unit, and said circuit connection information rewriting unit performs at least one of,

rewriting of circuit connection information of each of MOS transistors, other than an MOS transistor device having the smallest gate width, to information of parallel connection of MOS transistor devices, each having the smallest gate width, when gate lengths of the MOS transistor devices are equal to each other, in a group of the MOS transistor devices in the groups formed by said group coupling unit;

and

rewriting of circuit connection information of each of the MOS transistors, other than the MOS transistor device having the smallest gate length, to information of serial connection of MOS transistor devices each having the smallest gate length when gate widths of the MOS transistor devices are equal to each other, wherein said design constraint adding unit adds said device pairing constraint to the circuit connection information, including the circuit connection information rewritten by said circuit connection information rewriting unit.

10. An analog cell layout designing method comprising:

a circuit diagram generating step of generating an analog circuit diagram;

a circuit diagram data storing step of storing circuit diagram data corresponding to the analog circuit diagram generated in the circuit diagram generating step;

a circuit connection information extracting step of extracting circuit connection information from the stored analog circuit diagram data;

a first circuit connection information storing step of storing the circuit connection information extracted in the circuit connection information extracting step;

a design constraint predicting and extracting step of predicting and extracting devices to be paired from the stored circuit connection information and adding the devices extracted as design constraints to the circuit connection information;

a second circuit connection information storing step of storing the circuit connection information to which the design constraints are added in the design constraint predicting and extracting step;

an automatic placing step of placing layout cells selected based on the stored circuit connection information including the design constraints in accordance with a process design rule; and

an automatic routing step of conducting routing of the layout cells placed in the automatic placing step in accordance with the process design rule.

11. The analog cell layout designing method according to claim 10, wherein the design constraint predicting and extracting step comprises:

a node name giving step of giving a node name to a power supply line and a ground line in the stored circuit connection information stored;

a circuit connection information tree generating step of generating a circuit connection information tree using the power supply line to which the node name is given as a start point and indicative of a connection relation of P-type transistor devices and a connection relation of resistive elements, and generating a circuit connection tree using the ground line to which the node name is given as a start point and indicative of a connection relation of N-type transistor devices and a connection relation of resistive elements;

a grouping step of grouping devices of the same kind at the same level in each of the circuit connection information trees generated;

a group dividing step of dividing a group by selecting devices connected to the same line, other than the power supply line, or selecting devices connected to the same line, other than the ground line, from the devices in each of groups formed in the grouping step;

a group coupling step of coupling groups sharing a device in the groups formed in the group dividing step;

a design constraint adding step of adding the groups formed in the group dividing step, as a pairing constraint to the circuit connection information; and

an editing step of editing the device pairing constraint added in the design constraint adding step and storing the result of addition.

12. The analog cell layout designing method according to claim 11, wherein the design constraint predicting and extracting step further comprises a circuit connection information rewriting step of rewriting circuit connection information of each of the resistive elements, other than the resistive element having the lowest resistance, to information of serial connection of resistive elements each having the lowest resistance in a resistive element group in the groups formed in the group coupling step, wherein the design constraint adding step adds the device pairing constraint to the circuit connection information, including the circuit connection information rewritten in the circuit connection information rewriting step.

13. The analog cell layout designing method according to claim 11, wherein the design constraint predicting and extracting step further comprises a circuit connection information rewriting step of rewriting circuit connection information of each of bipolar transistor devices, other than a bipolar transistor device having the smallest emitter size, in a group of bipolar transistor devices in the groups formed in the group coupling step to information of parallel connection of the bipolar transistor devices, each having the smallest emitter size, wherein the design constraint adding step adds the device pairing constraint to the circuit connection information, including the circuit connection information rewritten in the circuit connection information rewriting step.

14. The analog cell layout designing step according to claim 11, wherein the design constraint predicting and extracting step further comprises a circuit connection information rewriting step of performing at least one of

rewriting of circuit connection information of each of MOS transistors, other than an MOS transistor device having the smallest gate width, to information of parallel connection of MOS transistor devices, each having the smallest gate width when gate lengths of the MOS transistor devices are equal to each other, in an MOS transistor device group in the groups formed in the group coupling step;

and

rewriting of circuit connection information of each of MOS transistors, other than an MOS transistor device having the smallest gate length, to information of serial connection of MOS transistor devices, each having the smallest gate length when gate widths of the MOS transistor devices are equal to each other, wherein the design constraint adding step adds the device pairing constraint to the circuit connection information, including the circuit connection information rewritten in the circuit connection information rewriting step.

15. The analog cell layout designing method according to claim 10, wherein the design constraint predicting and extracting step comprises:

a node name giving step of giving a node name to a power supply line and a ground line in the stored circuit connection information;

a circuit connection information tree generating step of generating a circuit connection information tree using the power supply line to which the node name is given as a start point and indicative of a connection relation of P-type transistor devices and a connection relation of resistive elements, and generating a circuit connection tree using the ground line to which the node name is given as a start point and indicative of a connection relation of N-type transistor devices and a connection relation of resistive elements;

a grouping step of grouping devices of the same kind at the same level in each of the circuit connection information trees generated;

a group dividing step of dividing a group by selecting devices connected to the same line, other than the power supply line, or selecting devices connected to the same line, other than the ground line, from the devices in each of groups formed in the grouping step;

a branch device grouping step, when a branch extending from the power supply line to the ground line and a branch extending from the ground line to the power supply line exist in each of the circuit connection information trees generated, of grouping all the devices of the same kind existing in each of the branches;

a group coupling step of coupling groups sharing a device in groups formed in the group dividing step and groups formed in the branch device grouping step;

a design constraint adding step of adding each of the groups formed in the group dividing step and the groups formed in the branch device grouping step as a device pairing constraint to the circuit connection information; and

an editing step of editing the device pairing constraint added in the design constraint adding step and storing the result of addition.

16. The analog cell layout designing method according to claim 15, wherein the design constraint predicting and extracting step further comprises a circuit connection information rewriting step of rewriting circuit connection information of each of the resistive elements, other than the resistive element having the lowest resistance, to information of serial connection of resistive elements each having the lowest resistance in a resistive element group in the groups formed in the group coupling step, wherein the design constraint adding step adds the device pairing constraint to the circuit connection information, including the circuit connection information rewritten in the circuit connection information rewriting step.

17. The analog cell layout designing method according to claim 15, wherein the design constraint predicting and extracting step further comprises a circuit connection information rewriting step of rewriting circuit connection information of each of bipolar transistor devices, other than a bipolar transistor device having the smallest emitter size, in a group of bipolar transistor devices in the groups formed in the group coupling step to information of parallel connection of the bipolar transistor devices, each having the smallest emitter size, wherein the design constraint adding step adds the device pairing constraint to the circuit connection information, including the circuit connection information rewritten in the circuit connection information rewriting step.

18. The analog cell layout designing step according to claim 15, wherein the design constraint predicting and extracting step further comprises a circuit connection information rewriting step of performing at least one of

rewriting of circuit connection information of each of MOS transistors, other than an MOS transistor device having the smallest gate width, to information of parallel connection of MOS transistor devices, each having the smallest gate width when gate lengths of the MOS transistor devices are equal to each other, in an MOS transistor device group in the groups formed in the group coupling step;

and

rewriting of circuit connection information of each of MOS transistors, other than an MOS transistor device having the smallest gate length, to information of serial connection of MOS transistor devices, each having the smallest gate length when gate widths of the MOS transistor devices are equal to each other, wherein the design constraint adding step adds the device pairing constraint to the circuit connection information, including the circuit connection information rewritten in the circuit connection information rewriting step.

19. A computer program for causing a computer to perform:

a circuit diagram generating step of generating an analog circuit diagram;

a circuit diagram data storing step of storing circuit diagram data corresponding to the analog circuit diagram generated in the circuit diagram generating step;

a circuit connection information extracting step of extracting circuit connection information from the stored analog circuit diagram data;

a first circuit connection information storing step of storing the circuit connection information extracted in the circuit connection information extracting step;

a design constraint predicting and extracting step of predicting and extracting devices to be paired from the stored circuit connection information and adding the devices extracted as design constraints to the circuit connection information;

a second circuit connection information storing step of storing the circuit connection information to which the design constraints are added in the design constraint predicting and extracting step;

an automatic placing step of placing layout cells selected on the basis of the stored circuit connection information including the design constraints in accordance with a process design rule; and

an automatic routing step of conducting routing of the layout cells placed in the automatic placing step in accordance with the process design rule.