Salicided gate for virtual ground arrays

• US 6,645,801 B1
• Filed: 10/01/2001
• Issued: 11/11/2003
• Est. Priority Date: 10/01/2001
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Ramsbey, Mark T., Sun, Yu, Chang, Chi
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): Gebremariam, Samuel A
• Application Number:
  US09/968,456
• Time in Patent Office: 771 Days
• Field of Search: 438/261, 438/216, 438/591, 438/593, 438/655, 438/258
• US Class Current: 438/216
• CPC Class Codes: H01L 21/76889 by forming silicides of refractory metals
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The present invention provides a process for saliciding the word lines in a virtual ground array flash memory device without saliciding the substrate between word lines. According to the invention, in a process for manufacturing virtual ground array flash memory devices, a salicide protect layer covers the substrate between word lines in the core region while the tops of the word lines are exposed. The salicide protect layer can be brought into the desired configuration by one or more of masking the substrate between word lines during an etching process, removing salicide protection material in the core by polishing, and forming a comparatively thick layer of salicide protection material in the core whereby the tendency of the salicide protect layer to follow the contour of the underlying structures is reduced. With the substrate between word lines protected by the salicide protect layer, the word lines are salicided. The process of the invention produces virtual ground array flash memory devices with salicided word lines, but without shorting between bit lines.

Claims

1. A method of forming a virtual ground array non-volatile semiconductor memory device, comprising:

providing a semiconductor substrate, the semiconductor substrate having a core region and a peripheral region;

forming charge trapping layers comprising at least one dielectric layer over the core region;

forming a poly layer over at least the charge trapping layers;

patterning the poly layer in the core region thereby forming adjacent word lines without bit line contacts therebetween having a first spacing and forming adjacent word lines with bit line contacts therebetween having a second spacing, the second spacing being wider than the first spacing;

providing one or more salicide protect layers over the core region;

removing a portion of the one or more salicide protect layers to expose the word lines, without exposing the substrate in the spaces between word lines; and

saliciding the word lines.

2. The method of claim 1, wherein the locations for bit line contacts are masked during at least a portion of the process of removing a portion of the one or more salicide protect layers.

3. The method of claim 1, wherein the one or more salicide protect layers comprise a material used to form spacers in the peripheral region.

4. The method of claim 1, wherein removing a portion of the one or more salicide protect layers comprises polishing.

5. The method of claim 4, wherein the word lines are exposed by polishing.

6. The method of claim 1, wherein removing a portion of the one or more salicide protect layers comprises etching.

7. The method of claim 1, wherein the charge trapping layers and the poly layer form a memory cell stack in the core region and the one or more salicide protect layers are provided with a thickness greater than or about equal to a thickness of the memory cell stack.

8. The method of claim 7, wherein the process of removing a portion of the one or more salicide protect layers comprises polishing.

9. The method of claim 1, wherein the core region comprises buried bit lines.

10. The method of claim 9, wherein the virtual ground array non-volatile semiconductor memory device has a NOR device structure.

11. The method of claim 1, wherein the virtual ground array non-volatile semiconductor memory device comprises a SONOS memory device.

12. The method of claim 1, further comprising

masking the core region; and

while the core region is masked and prior to saliciding the word lines, doping the substrate to form source and drain regions adjacent gates in the peripheral region.

13. The method of claim 12, wherein source and drain regions adjacent gates in the periphery are salicided at the same time as the word lines in the core region.

14. The method of claim 1, wherein the substrate is provided without oxide islands between word lines in the core region and oxide islands are not formed between word lines in the core region.

15. A method of forming a virtual ground array non-volatile semiconductor memory device, comprising:

providing a semiconductor substrate having a core region and a peripheral region;

forming charge trapping layers comprising at least one dielectric layer over the core region;

forming a poly layer over at least the charge trapping layers;

patterning the poly layer in the core region thereby forming adjacent word lines without bit line contacts therebetween having a first spacing and forming adjacent word lines with bit line contacts therebetween having a second spacing, the second spacing being wider than the first spacing; and

while at least one of the charge trapping layers covers the bit line contacts, saliciding the word lines.

16. The method of claim 15, wherein the substrate is provided without oxide islands between word lines in the core region and oxide islands are not formed between word lines in the core region.

17. The method of claim 15, further comprising providing a salicide protect layer over the core region after patterning the poly layer in the core region.

18. The method of claim 15, wherein all of the charge trapping layers cover the bit line contacts while the word lines are salicided.

19. The method of claim 15, wherein the locations for bit line contacts are masked while one or more of the charge trapping layers are removed.

20. The method of claim 15, wherein the virtual ground array non-volatile semiconductor memory device has a NOR device structure.

21. The method of claim 15, wherein the virtual ground array non-volatile semiconductor memory device comprises a SONOS memory device.

22. The method of claim 15, further comprising

masking the core region; and

while the core region is masked and prior to saliciding the word lines, doping the substrate to form source and drain regions of gates in the peripheral region.

23. The method of claim 22, wherein source and drain regions adjacent gates in the periphery are salicided at the same time as the word lines in the core region.

24. A method of forming a virtual ground array non-volatile semiconductor memory device, comprising:

providing a semiconductor substrate, the semiconductor substrate having a core region and a peripheral region;

forming charge trapping ONO dielectric over the core region;

forming a poly layer over at least the charge trapping ONO dielectric;

patterning the poly layer in the core region thereby forming adjacent word lines without bit line contacts therebetween having a first spacing and forming adjacent word lines with bit line contacts therebetween having a second spacing, the second spacing being wider than the first spacing;

providing one or more salicide protect layers over the core region;

removing a portion of the one or more salicide protect layers to expose the word lines, without exposing the substrate in the spaces between word lines; and

saliciding the word lines.

25. The method of claim 24, wherein the locations for bit line contacts are masked during at least a portion of the process of removing a portion of the one or more salicide protect layers.

26. The method of claim 24, wherein the word lines are exposed by polishing.

27. The method of claim 24, wherein removing a portion of the one or more salicide protect layers comprises etching.

28. The method of claim 24, wherein the core region comprises buried bit lines.

29. The method of claim 24, further comprising

masking the core region; and

while the core region is masked and prior to saliciding the word lines, doping the substrate to form source and drain regions adjacent gates in the peripheral region.

30. The method of claim 24, wherein the substrate is provided without oxide islands between word lines in the core region and oxide islands are not formed between word lines in the core region.