Focal plane averaging implementation for CMOS imaging arrays using a split photodiode architecture

• US 6,646,245 B2
• Filed: 01/22/1999
• Issued: 11/11/2003
• Est. Priority Date: 01/22/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Nair, Raj
• Primary Examiner(s): Luu, Thanh X.
• Application Number:
  US09/234,857
• Publication Number:
  US 20020011551A1
• Time in Patent Office: 1,754 Days
• Field of Search: 250/208--20, 250/226, 348/315, 345/90-93
• US Class Current: 250/208.1
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers

Abstract

A photosensor structure including pixel areas. Each pixel area represents an electrical pixel. The photosensor structure also has a predetermined number of quadrants. Each is positioned in a corner of one of the pixel areas. Each quadrant belongs to different optical pixels.

Claims

1. A system comprising:

an imaging device comprising;

a plurality of photo-sensing devices arranged into Quadrants to form an array; and

a circuit to generate a plurality of pixel signals each being a focal plane average of signals generated by said Quadrants of photo-sensing devices, wherein said circuit comprises;

a first switching device to simultaneously transmit changes to said quadrants of photo-sensing devices to form said pixel signal;

a storage node to store said pixel signal;

a second switching device to selectively couple said quadrant of photo-sensing devices to said storage node;

a third switching device to selectively couple said storage node to a bitline; and

a interpolator to generate a color value from each of said pixel signal.

2. The system of claim 1, further comprising a plurality of metal lines configured to line along a central axis of each of said Quadrants of photo-sensing devices.

3. The system of claim 1, wherein said circuit comprises capacitance elements to respectively store said pixel signals.

4. The system of claim 3, wherein said capacitance elements each comprise a gate capacitance of a field effect transistor.

5. The system of claim 3, wherein said second switching device to selectively couple a distinct combination of photo-sensing devices to a corresponding capacitance element.

6. The system of claim 1, wherein said third switching device to output said pixel signal in response to an enable signal.

7. The system of claim 1, further comprising a compression unit to compress data associated with each color value generated by said interpolator.