Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates

• US 6,646,293 B2
• Filed: 07/18/2001
• Issued: 11/11/2003
• Est. Priority Date: 07/18/2001
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Holmes, John E., Rockwell, Stephen Kent, Emrick, Rudy M.
• Primary Examiner(s): Wille, Douglas A.
• Application Number:
  US09/906,783
• Publication Number:
  US 20030017683A1
• Time in Patent Office: 846 Days
• Field of Search: 257/194
• US Class Current: 257/194
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 29/66318 Heterojunction transistors
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7371 Vertical transistors
• CPC Class Codes: H01L 29/7783 using III-V semiconductor material

Abstract

High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Once such a structure is built, a high electron mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT) can be constructed on the structure. A HEMT or HBT of the above structure can then be used in a switch or in an amplifier.

Claims

1. A transistor comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying the monocrystalline silicon substrate;

an amorphous perovskite oxide material overlying the amorphous oxide material;

a monocrystalline compound semiconductor material overlying the amorphous perovskite oxide material; and

a high electron mobility transistor formed using the monocrystalline compound semiconductor material.

2. A high electron mobility transistor comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying the monocrystalline silicon substrate;

an amorphous perovskite oxide material overlying the amorphous oxide material; and

a monocrystalline compound semiconductor material overlying the amorphous perovskite oxide material;

a layer of undoped GaAs overlying the monocrystalline compound semiconductor material;

a layer of undoped AlGaAs overlying the layer of undoped GaAs;

a layer of n−

AlGaAs overlying the layer of undoped n−

AlGaAs;

a layer of n+ GaAs overlying the layer of n−

AlGaAs;

a source of said transistor and a drain of said transistor overlying the layer of n+ GaAs; and

a gate of said transistor overlying the layer of n−

AlGaAs.

3. The transistor of claim 2 wherein said gate is a Schottky barrier.

4. The transistor of claim 2 wherein said drain and said source are constructed of ohmic materials.

5. A high electron mobility transistor comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying the monocrystalline silicon substrate;

an amorphous perovskite oxide material overlying the amorphous oxide material; and

a monocrystalline compound semiconductor material overlying the amorphous perovskite oxide material;

a layer of undoped AlGaAs overlying the monocrystalline compound semiconductor material;

a layer of undoped GaAs overlying the layer of undoped AlGaAs;

a layer of undoped AlGaAs overlying the layer of undoped GaAs;

a layer of n−

GaAs overlying the layer of undoped AlGaAs;

a layer of undoped AlGaAs overlying the layer of n−

GaAs;

a layer of undoped GaAs overlying the layer of undoped AlGaAs;

a layer of undoped AlGaAs overlying the layer of undoped GaAs;

a layer of n−

AlGaAs overlying the layer of undoped AlGaAs;

a layer of n−

GaAs overlying the layer of n−

AlGaAs;

a source of said transistor and a drain of said transistor overlying the layer of n−

GaAs; and

a gate of said transistor overlying the layer of n−

AlGaAs.

6. The transistor of claim 5 wherein said gate is a Schottky barrier.

7. The transistor of claim 5 wherein said drain and said source are constructed of ohmic materials.