Grounded body SOI SRAM cell
First Claim
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1. A semiconductor memory device comprising:
- an SOI substrate having a thin silicon layer on top of a buried insulator;
an SRAM comprising two I/O NFETs, two latch NFETs and two latch PFETs located in said thin silicon layer, each said I/O NFET, latch NFET and latch PFET having a body region between a source region and a drain region; and
a first connecting region in said thin silicon layer abutting the source and body regions of each said I/O NFETS, said first connecting region electrically connected to ground.
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Abstract
A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, wherein the bodies of two of the NFETs are electrically connected to ground. Additionally, the bodies of the two PFETs are electrically connected to VDD.
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Citations
11 Claims
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1. A semiconductor memory device comprising:
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an SOI substrate having a thin silicon layer on top of a buried insulator;
an SRAM comprising two I/O NFETs, two latch NFETs and two latch PFETs located in said thin silicon layer, each said I/O NFET, latch NFET and latch PFET having a body region between a source region and a drain region; and
a first connecting region in said thin silicon layer abutting the source and body regions of each said I/O NFETS, said first connecting region electrically connected to ground. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor memory device comprising:
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an SOI substrate having a thin silicon layer on top of a buried insulator;
an SRAM comprising two I/O NFETs, two latch NFETs and two latch PFETs located in said thin silicon layer, each said I/O NFET, latch NFET and latch PFET having a body region between a source region and a drain region;
a first connecting region in said thin silicon layer, said first connecting region electrically connected to ground; and
a pair of second connecting regions in said thin silicon layer, each second connecting region co-extensive with one of said body regions of said I/O NFETs and between said body regions and said first connecting region. - View Dependent Claims (7, 8, 9, 10, 11)
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Specification