Wide bandwidth, current sharing, MOSFET audio power amplifier with multiple feedback loops

• US 6,646,508 B1
• Filed: 05/03/2002
• Issued: 11/11/2003
• Est. Priority Date: 12/30/1996
• Status: Expired due to Fees

• Current Assignee: Anthony T. Barbetta
• Original Assignee: Anthony T. Barbetta
• Inventors: Barbetta, Anthony T.
• Primary Examiner(s): Mottola, Steven J.
• Application Number:
  US10/139,037
• Time in Patent Office: 557 Days
• Field of Search: 330/264, 330/265, 330/267, 330/269, 330/270, 330/271, 330/301
• US Class Current: 330/264
• CPC Class Codes: H03F 1/086 with FET's
• CPC Class Codes: H03F 1/342 in field-effect transistor amplifiers
• CPC Class Codes: H03F 3/265 with field-effect transistors only
• CPC Class Codes: H03F 3/3018 using opamps as driving stages

Abstract

The disclosure describes a phase-splitter/level shifter comprising a first MOS transistor has a drain coupled to the first output node and a source coupled to a feedback node through a source resistor and a gate. A second MOS transistor has a drain coupled to a second output node and a source coupled to the feedback node through a source resistor and a gate. A first operational amplifier has a non-inverting input coupled to a single-ended input node, and an inverting input coupled to a second reference current source, an output coupled to the gate of the first MOS transistor. A second operational amplifier has a non-inverting input coupled to a single-ended input node, an inverting input coupled to a first reference current source, and an output coupled to the gate of the second MOS transistor. A variable resistor is coupled between the source of the first and second MOS transistor.

Claims

1. A phase-splitter/level shifter comprising:

a single-ended input node;

a feedback node coupled to ground through a shunt resistor;

first and second complimentary output nodes;

first and second complimentary power supply rails;

a first load resistor coupled between said first power supply rail and said first output node;

a second load resistor coupled between said second power supply rail and said second output node;

a first MOS transistor having a drain coupled to said first output node, a source coupled to said feedback node through a source resistor and a gate;

a second MOS transistor having a drain coupled to said second output node, a source coupled to said feedback node through a source resistor and a gate;

first and second complimentary reference current sources;

a first operational amplifier having a non-inverting input coupled to said single-ended input node, an inverting input coupled to said second reference current source, and an output coupled to said gate of said first MOS transistor;

a second operational amplifier having a non-inverting input coupled to said single-ended input node, an inverting input coupled to said first reference current source, and an output coupled to said gate of said second MOS transistor; and

a variable resistor coupled between said source of said first MOS transistor and said second MOS transistor.