Memory system having programmable multiple and continuous memory regions and method of use thereof

• US 6,646,646 B2
• Filed: 12/13/2000
• Issued: 11/11/2003
• Est. Priority Date: 12/13/2000
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Peterson, James R., Radke, William
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US09/737,231
• Publication Number:
  US 20020070941A1
• Time in Patent Office: 1,063 Days
• Field of Search: 345/501-506, 345/519-520, 345/522, 345/530-574, 711/170-173, 711/154, 711/202
• US Class Current: 345/543
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G09G 2360/12 Frame memory handling
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

A memory system and method for allocating and accessing memory. The memory system includes first and second addressable memory regions coupled to a memory controller. The memory controller includes a register to store a respective offset value and values defining portions of the first and second addressable memory regions allocated to first and second logical memory spaces. A first portion of the first addressable memory region is allocated to a first requested memory space, and a second portion of the first addressable memory region is allocated to a second requested memory space. Any remaining portions of the first and second requested memory spaces are remapped to the second addressable memory region. The memory controller is adapted to access the first addressable memory region in response to receiving a memory address for a location within the first portions of the first and second memory spaces and to access the second addressable memory region in response to receiving a memory address for a location within the second portions of the first and second memory spaces.

Claims

1. A method of allocating and accessing a memory having first and second addressable memory regions, the method comprising:

separating logical memory addresses of first and second allocated memory spaces into first and second portions;

allocating the first portions of the first and second memory spaces to the first addressable memory region and allocating the second portions of the first and second memory spaces to the second addressable memory region; and

remapping memory access requests to the second portion of the first and second memory spaces to the second addressable memory region.

2. The method of claim 1, further comprising storing values defining the first and second portions of the first and second memory spaces.

3. The method of claim 1 wherein separating logical memory addresses comprises allocating the memory of the first addressable memory region to the first portions of the first and second allocated memory spaces an allocating any remainder of the first and second allocated memory spaces to the second addressable memory region.

4. The method of claim 1 wherein the first addressable memory region comprises first and second embedded memory arrays.

5. The method of claim 4 wherein allocating the first portions of the first and second memory spaces comprises allocating the first embedded memory array to the first portion of the first memory space and the second embedded memory array to the first portion of the second memory space.

6. The method of claim 1 wherein remapping memory access requests comprises adding an offset value to a requested address and accessing the memory location of the resulting address.

7. The method of claim 1 wherein the first portions of the first and second allocated memory spaces are defined by a start address value, a size value, and an embedded size value.

8. A method of allocating memory having first and second addressable memory regions that are logically contiguous, the method comprising:

allocating a first portion of the first addressable memory region to a first requested memory space, and a second portion of the first addressable memory region to a second requested memory space; and

mapping any remaining portions of the first and second requested memory space to the second addressable memory region.

9. The method of claim 8, further comprising storing values defining the first and remaining portions of the first and second requested memory spaces.

10. The method of claim 8 wherein the first addressable memory region comprises first and second embedded memory arrays.

11. The method of claim 10 wherein allocating the portions of the first memory space comprises allocating the first embedded memory array to the first requested memory space and the second embedded memory array to the second requested memory space.

12. The method of claim 8 wherein mapping any remaining portions comprises adding an offset value to a requested address and accessing the memory location of the resulting address.

13. The method of claim 8 wherein allocating portions of the first addressable memory region comprises storing a start address value, a size value, and an embedded size value for the first and second requested memory spaces.

14. A memory sub-system for a graphics processing system, comprising:

first and second addressable memory regions; and

a memory controller coupled to the first and second addressable memory regions and having a register to store for first and second logical memory spaces a respective offset value and values defining first and second portions for the respective memory space, the memory controller adapted to access the first addressable memory region in response to receiving a memory address for a location within the first portions of the first and second memory spaces and to access the second addressable memory region in response to receiving a memory address for a location within the second portions of the first and second memory spaces.

15. The memory sub-system of claim 14 wherein the first addressable memory comprises an embedded memory included in the graphics processing system.

16. The memory sub-system of claim 15 wherein the embedded memory comprises first and second embedded memory arrays.

17. The memory sub-system of claim 14 wherein the values defining the first and second portions for the respective memory space stored by the register comprise a start address, a size address, a size value, and an embedded size value.

18. The memory sub-system of claim 14, further comprising a third addressable memory coupled to the memory controller.

19. A memory sub-system for a graphics processing system, comprising:

first and second addressable memory regions;

a register to store values defining first and second portions of a first memory space and first and second portions of a second memory space, and an offset value for each memory space; and

a memory controller coupled to the register and to the first and second addressable memory regions, the memory controller adapted to access the first and second addressable memory regions and in response to receiving a requested memory address corresponding to a logical memory address in the second portion of the first or second memory spaces, add the respective offset value to the requested memory address and access the resulting memory location.

20. The memory sub-system of claim 19 wherein the first addressable memory comprises an embedded memory included in the graphics processing system.

21. The memory sub-system of claim 20 wherein the embedded memory comprises first and second embedded memory arrays.

22. The memory sub-system of claim 19 wherein the values stored by the register comprise a start address, a size value, and an embedded size value.

23. The memory sub-system of claim 19, further comprising a third addressable memory coupled to the memory controller.

24. A memory system for storing graphics data in a computer graphics processing system, comprising:

a plurality of memory arrays having memory locations corresponding to memory addresses;

a register to store values defining allocation of the plurality of memory arrays to first and second portions of a first memory space and first and second portions of a second memory space, the register further storing an offset value for each memory space; and

a plurality of memory controllers corresponding to the plurality of memory arrays, each memory controller coupled to a memory controller bus on which memory addresses can be passed from one memory controller to the other and coupled to query the register for the stored values, each memory controller further coupled to a respective memory array and adapted to add in response to receiving a requested memory address corresponding to a logical memory address in the second portion of the first or second memory spaces a respective offset value to the requested memory address and provide the resulting address to the memory controller coupled to the memory array including the memory location corresponding to the resulting address.

25. The memory system of claim 24 wherein the plurality of memory arrays comprises at least two embedded memory arrays included in the graphics processing system.

26. The memory system of claim 24 wherein the values stored by the register for each memory array comprise a start address, a size value, and an embedded size value.

27. The memory system of c aim 24 wherein the plurality of memory arrays comprises first and second embedded memory arrays, and a local memory array, the register having values defining the allocation of the first embedded memory array to the first portion of the first memory space, the second embedded memory array to the first portions of the second memory space, and the local memory array to the second portions of the first and second memory spaces.

28. A graphics processing system, comprising:

a bus interface for coupling to a system bus;

a graphics processor coupled to the bus interface to process graphics data;

address and data busses coupled to the graphics processor to transfer address and graphics data to and from the graphics processor;

display logic coupled to the data bus to drive a display;

a memory request bus coupled to the data bus to drive a display;

access requests; and

a memory system coupled to the data bus to store and retrieve data, the memory system comprising;

first and second addressable memory regions; and

a memory controller coupled to the first and second addressable memory regions and having a register to store for first and second logical memory spaces a respective offset value and values defining first and second portions for the respective memory space, the memory controller adapted to access the first addressable memory region in response to receiving a memory address for a location within the first portions of the first and second memory spaces and to access the second addressable memory region in response to receiving a memory address for a location within the second portions of the first and second memory spaces.

29. The graphics processing system of claim 28 wherein the first addressable memory comprises an embedded memory included in the graphics processing system.

30. The graphics processing system of claim 29 wherein the embedded memory comprises first and second embedded memory arrays.

31. The graphics processing system of claim 28 wherein the values defining the first and second portions for the respective memory space stored by the register comprise a start address, a size value, and an embedded size value.

32. The graphics processing system of claim 28, further comprising a third addressable memory coupled to the memory controller.

33. A computer system, comprising:

a system processor;

a system bus coupled to the system processor;

a system memory coupled to the system bus; and

a graphics processing system coupled to the system bus, the graphics processing system, comprising;

a bus interface for coupling to the system us;

a graphics processor coupled to the bus interface to process graphics data;

address and data busses coupled to th graphics processor to transfer address and graphics data to and from the graphics processor;

display logic coupled to the data bus to drive a display;

a memory request bus coupled to the graphics processor to transfer memory access requests; and

a memory system coupled to the data bus to store and retrieve data, the memory system comprising;

first and second addressable memory regions; and

a memory controller coupled to he first and second addressable memory regions and having a register to store for first and second logical memory spaces a respective offset value and values defining first and second portions for the respective memory space, the memory controller adapted to access the first addressable memory region in response to receiving a memory address for a location within the first portions of the first and second memory spaces and to access the second addressable memory region in response to receiving a memory address for a location within the second portions of the first and second memory spaces.

34. The computer system of claim 33 wherein the first addressable memory comprises an embedded memory included in the graphics processing system.

35. The computer system of claim 34 wherein the embedded memory comprises first and second embedded memory arrays.

36. The computer system of claim 33 wherein the values defining the first and second portions for the respective memory space stored by the register comprise a start address, a size value, and embedded size value.

37. The computer system of claim 33, further comprising a third addressable memory coupled to the memory controller.