Multipath parameter estimation in spread-spectrum communications systems

• US 6,647,077 B1
• Filed: 07/31/2000
• Issued: 11/11/2003
• Est. Priority Date: 07/31/2000
• Status: Active Grant

• Current Assignee: Qualcomm technologies international, ltd. (Qualcomm, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: King, Eric J., Shan, Peijun
• Primary Examiner(s): Liu, Shuwang
• Application Number:
  US09/628,996
• Time in Patent Office: 1,198 Days
• Field of Search: 375/341, 375/346, 375/347, 375/348, 375/349, 375/130, 375/136, 375/140, 375/147, 370/206, 370/335
• US Class Current: 375/346
• CPC Class Codes: H04B 1/7113 Determination of path profile
• CPC Class Codes: H04B 1/7115 Constructive combining of multi-path signals, i.e. RAKE receivers
• CPC Class Codes: H04B 1/7117 Selection, re-selection, allocation or re-allocation of paths to fingers, e.g. timing offset control of allocated fingers
• CPC Class Codes: H04B 1/7183 Synchronisation

Abstract

A training circuit includes resources for processing magnitude and phase information received in a main propagation path signal with magnitude and phase information concurrently received in a secondary propagation path signal to determine values for magnitude, phase, and time offset of the secondary propagation path signal relative to the main propagation path signal. Differential decoding circuitry within the training circuit provides a correlation circuit, also in the training circuit, with differentially decoded sequences of symbol phase values derived from concurrent main and secondary signal propagation path symbol phase value sequences provided to the training circuit by an associated communications receiver. Operating on theses phase value sequences, the correlation circuit determines the time offset between the main and secondary propagation path signals based on determining the correspondence between symbol phase values received via the main propagation path signal and those concurrently received via the secondary propagation path signal. The training circuit can identify time offsets less than or greater than a symbol period, for either leading or lagging secondary path time offsets. A phase difference circuit, further included in the training circuit, determines a phase offset for the secondary propagation path signal relative to the main propagation path signal using main and secondary propagation path symbol phase values in combination with the time offset information. The relative magnitude, phase, and time information represents a characterization of the secondary propagation path with respect to the main propagation path. This characterization information may be used to improve reception performance or cancel multipath interference.

Claims

1. An apparatus for characterizing a secondary path signal relative to a main path signal received in a multipath radio signal, said apparatus comprising:

main and secondary magnitude inputs adapted to receive main and secondary magnitude values from the main and secondary path signals;

a magnitude comparator adapted to receive the main and secondary magnitude values and to determine a magnitude of the secondary path signal relative to the main path signal;

main and secondary phase inputs adapted to receive main and secondary symbol values from the main and secondary path signals;

first main and secondary delay elements adapted to receive the main and secondary symbol values and to output delayed main and secondary symbol values;

main and secondary differential decoders adapted to receive the main and secondary symbol values and the delayed main and secondary values and to output differentially decoded main and secondary symbol values;

second main and secondary delay elements adapted to receive the differentially decoded main and secondary symbol values and to output delayed differentially decoded main and secondary symbol values;

a correlator adapted to receive the differentially decoded main and secondary symbol values and the delayed differentially decoded main and secondary symbol values, and to determine a time offset of the secondary path signal relative to the main path signal based on identifying a symbol correspondence between the differentially decoded main and secondary symbol values; and

a phase comparator adapted to received the main and secondary symbol values and the delayed main and secondary symbol values and to determine a phase difference between corresponding main and secondary symbol values based, in part, on said symbol correspondence.

2. The apparatus of claim 1 wherein said magnitude comparator comprises main and secondary magnitude value accumulators and an associated comparator circuit adapted to output a relative magnitude value based on comparing accumulated main and secondary magnitude values.

3. The apparatus of claim 2 wherein said comparator circuit is adapted to compute a ratio between an accumulated secondary magnitude value and an accumulated main magnitude value.

4. The apparatus of claim 2 wherein said main and secondary magnitude value accumulators provide an accumulated main magnitude value and an accumulated secondary magnitude value based on integrating a number of received main and secondary magnitude values.

5. The apparatus of claim 1 wherein said correlator comprises:

a plurality of input circuits adapted to receive selected combinations of the differentially decoded main and secondary symbol values and the delayed differentially decoded main and secondary symbol values and to output a corresponding plurality of difference values;

a plurality of accumulators adapted to receive said difference values and to output a corresponding plurality of accumulated difference values; and

a correlation circuit adapted to receive said accumulated difference values and to identify one of said accumulated difference values as a minimum difference value, and further adapted to identify said symbol correspondence between main symbol values and secondary symbol values based on said minimum difference value.

6. The apparatus of claim 5 wherein said plurality of input circuits comprise:

a first input circuit adapted to receive a differentially decoded main symbol value and a delayed differentially decoded secondary symbol value, and further adapted to output a first difference value indicating a difference between the differentially decoded main symbol values and the delayed differentially decoded secondary symbol value;

a second input circuit adapted to receive the differentially decoded main symbol value and a differentially decoded secondary symbol value and further adapted to output a second difference value indicating a difference between the differentially decoded main and secondary symbol values; and

a third input circuit adapted to receive a delayed differentially decoded main symbol value and the differentially decoded secondary symbol value and further adapted to output a third difference value indicating a difference between the delayed differentially decoded main symbol value and the differentially decoded secondary symbol value.

7. The apparatus of claim 6 wherein respective ones of said plurality of accumulators accumulate respective ones of said first, second, and third difference values to form first, second, and third accumulated difference values, and wherein one of said accumulated difference values will be a minimum accumulated difference value indicating a maximum main and secondary symbol value correlation associated with one of said selected combinations of the differentially decoded main and secondary symbol values and the delayed differentially decoded main and secondary symbol values received by said plurality of input circuits.

8. The apparatus of claim 7 wherein said maximum main and secondary symbol value correlation indicates whether a given secondary symbol value corresponds to a concurrently received main symbol value, to a main symbol value received more than one symbol time before said given received secondary symbol, or to a main symbol value received more than one symbol time after said given secondary symbol.

9. The apparatus of claim 1 wherein said phase comparator comprises:

a plurality of input circuits adapted to receive selected combinations of the main and secondary symbol values and the delayed main and secondary symbol values and to output a corresponding plurality of difference values; and

a phase selection circuit adapted to select one of said plurality of difference values for output as a phase offset value for the secondary path signal relative to the main path signal based on said symbol correspondence identified by said correlator.

10. The apparatus of claim 9 wherein said plurality of input circuits comprise:

a first input circuit adapted to receive a main symbol value and a delayed secondary symbol value, and further adapted to output a first difference value indicating a difference between the main symbol value and the delayed secondary symbol value;

a second input circuit adapted to receive the main symbol value and a secondary symbol value, and further adapted to output a second difference value indicating a difference between the main and secondary symbol values; and

a third input circuit adapted to receive a delayed main symbol value and the secondary symbol value, and further adapted to output a third difference value indicating a difference between the delayed main symbol value and the secondary symbol value.

11. The apparatus of claim 10 wherein said phase selection circuit outputs said phase offset value by selecting one of said first, second, and third difference values as representing a phase difference between corresponding main and secondary symbol values, wherein said corresponding main and secondary symbols are selected based on said symbol correspondence.

12. The apparatus of claim 1 further comprising a phase slicer adapted to receive main symbol values from the main path signal and to output sliced main symbol values for input to said main phase input, whereby said apparatus receives sliced main symbol values from the main path signal via said main phase input, and further wherein said phase slicer changes received main symbol values to closest matching nominal symbol values, wherein the possible nominal symbol values are defined by a modulation scheme associated with the main and secondary path signals.

13. The apparatus of claim 1 further comprising a phase slicer adapted to receive differentially decoded secondary symbol values and to output sliced differentially decoded secondary symbol values, whereby said second secondary delay element and said correlator receive sliced differentially decoded secondary symbol values, and whereby said correlator additionally receives delayed sliced differentially decoded secondary symbol values output from said second secondary delay element, wherein said phase slicer changes differentially decoded secondary symbol values to closest matching nominal symbol values, and wherein the possible nominal symbol values are defined by a modulation scheme associated with the main and secondary path signals.

14. An apparatus for characterizing a secondary path signal relative to a main path signal received in a multipath radio signal, said apparatus comprising:

a correlation circuit adapted to concurrently receive sequences of differentially decoded main and secondary symbol values from the main and secondary path signals, and further adapted to determine a time offset of the secondary path signal relative to the main path signal based on identifying a symbol correspondence between main and secondary symbol values by cross-correlating selected ones in the sequence of differentially decoded main symbol values with selected ones in the sequence of differentially decoded secondary symbol values;

a phase comparison circuit adapted to concurrently receive one or more main and secondary symbol values from the main and secondary path signals, and further adapted to determine a phase offset of the secondary path signal relative to the main path signal based on computing a number of phase differences between selected ones of the main symbol values and selected ones of the secondary symbol values, and further based on selecting one of said number of phase differences as said phase offset based on said time offset determined by said correlation circuit; and

a magnitude comparison circuit adapted to concurrently receive one or more main and secondary magnitude values from the main and secondary path signals, and further adapted to determine a relative magnitude of the secondary path signal relative to the main path signal based on comparing the one or more secondary magnitude values with the one or more main magnitude values;

said characterization of the secondary path signal provided based on said apparatus outputting said time offset, said phase offset, and said relative magnitude.

15. The apparatus of claim 14 wherein said correlation circuit includes main and secondary delay elements adapted to receive the concurrent sequences of differentially decoded main and secondary symbol values, said main and secondary delay elements further adapted to output delayed sequences of differentially decoded main and secondary symbol values for use in said cross-correlating selected ones in the sequence of differentially decoded main symbol values with selected ones in the sequence of differentially decoded secondary symbol values.

16. The apparatus of claim 15 wherein said correlation circuit performs said cross-correlating selected ones in the sequence of differentially decoded main symbol values with selected ones in the sequence of differentially decoded secondary symbol values by correlating selected ones in the delayed sequence of differentially decoded secondary symbol values with selected ones in the sequence of differentially decoded main symbol values to form a first correlation value, correlating respective ones in the sequences of differentially decoded main and secondary symbol values to form a second correlation value, and correlating selected ones in the sequence of differentially decoded secondary symbol values with selected ones in the sequence of delayed differentially decoded main symbol values to form a third correlation value.

17. The apparatus of claim 16 wherein said correlation circuit determines said time offset based on identifying one of said first, second, and third correlation values as representing a maximum symbol correlation, wherein said maximum symbol correlation indicates whether secondary path signal leads the main path signal by a time offset in the range of one to two symbol times, lags the main path signal by a time offset in the range of one to two symbol times, or is aligned within one symbol time of the main path signal.

18. The apparatus of claim 17 wherein said phase comparison circuit determines said phase offset based on computing leading, lagging, and concurrent phase differences between the one or more main and secondary symbol values to form said number of phase differences, with said phase offset selected as one of said number of phase differences based on said time offset.

19. The apparatus of claim 15 wherein said correlation circuit performs said cross-correlating selected ones in the sequence of differentially decoded main symbol values with selected ones in the sequence of differentially decoded secondary symbol values by correlating selected ones in the delayed sequence of differentially decoded secondary symbol values with selected ones in the sequence of differentially decoded main symbol values to form a number of leading correlation values, correlating respective ones in the main and secondary symbol sequences to form a concurrent correlation value, and by correlating selected ones in the sequence of differentially decoded secondary symbol values with selected ones in the delayed sequence of differentially decoded main symbol values to form a number of lagging correlation values.

20. The apparatus of claim 19 wherein said correlation circuit identifies said symbol correspondence and determines said time offset based on identifying one of said leading, lagging, and concurrent correlation values as representing a maximum symbol correlation, wherein said maximum symbol correlation indicates the number of symbol times by which the secondary path signal leads or lags the main path signal, or indicates that the secondary path signal is aligned within one symbol time of the main path signal.

21. The apparatus of claim 20 wherein said phase comparison circuit determines said phase offset based on computing leading, lagging, and concurrent phase differences between the one or more main and secondary symbol values to form said number of phase differences, with said phase offset selected as one of said number of phase differences based on said time offset.

22. The apparatus of claim 14 wherein said magnitude comparison circuit comprises main and secondary magnitude value accumulators adapted to accumulate one or more magnitude values from the main and secondary path signals to form accumulated main and secondary magnitudes, and further comprising a magnitude comparator adapted to output said relative magnitude based on comparing the accumulated main and secondary magnitudes.

23. The apparatus of claim 22 wherein said main and secondary magnitude value accumulators function as integrators and wherein said accumulated main and secondary magnitudes represent an integration of a number of main and secondary magnitude values.

24. An apparatus for characterizing a secondary path signal relative to a main path signal received in a multipath radio signal, said apparatus comprising:

a means for receiving sequences of main and secondary symbol values concurrently extracted from the main and secondary path signals;

a means for generating sequences of differentially decoded main and secondary symbol values based on differentially decoding the sequences of main and secondary symbol values;

a means for determining a symbol offset based on identifying corresponding symbol values between the sequences of differentially decoded secondary symbol values and differentially decoded main symbol values;

a means for determining a time offset between the main and secondary path signals based on said symbol offset and a known symbol period;

a means for determining a number of phase differences between selected ones in the sequences of main and secondary symbols values;

a means for selecting one of said number of phase differences as a relative phase offset based on said symbol offset;

a means for receiving sequences of main and secondary symbol magnitudes concurrently extracted from the received main and secondary path signals;

a means for accumulating main and secondary symbol magnitudes; and

a means for comparing accumulated main and secondary symbol magnitudes to determine a relative magnitude for the secondary path signal to the main path signal; and

means of outputting a set of characterization values including said relative magnitude, said relative phase offset, and said time offset.