Multifunction device with register space for individually enabling or disabling a function of plurality of functions in response to function configuration

• US 6,647,434 B1
• Filed: 12/28/1999
• Issued: 11/11/2003
• Est. Priority Date: 12/28/1999
• Status: Expired due to Term

• Current Assignee: Dell USA LP (Dell Technologies Inc.)
• Original Assignee: Dell USA LP (Dell Technologies Inc.)
• Inventors: Kamepalli, Srinivas R.
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): PEYTON, TAMMARA R
• Application Number:
  US09/473,284
• Time in Patent Office: 1,414 Days
• Field of Search: 710/8, 710/10, 710/14, 710/104, 713/1, 713/2, 713/100, 713/324
• US Class Current: 710/14
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
• CPC Class Codes: G06F 9/4411 Configuring for operating with peripheral devices; Loading of device drivers

Abstract

A system for individually disabling a function of a multifunction device located on a computer bus of a computer system. In one example, the multifunction device is located on a computer bus conforming to a PCI local bus standard and the multifunction device is a PCI compliant device. The multifunction device includes at least one register that stores configuration information regarding which functions are disabled. In response to a bus command addressed to a function, the configuration information is read to determine whether the function is disabled. The configuration information may be stored in the device dependent region of a configuration register space associated with each function. A function can be enabled or disabled by changing the configuration information stored in the multifunction device. Writes to change the configuration information may be made during a computer system BIOS startup routine or may be made by utilizing a configuration utility of the computer system'"'"'s operating system. In some systems, the configuration information stored in a register space of each function includes information regarding the enablement or disablement of the other functions of the multifunction device.

Claims

1. A computer system comprising:

at least one system processor;

a computer bus, the at least one system processor operably coupled to the computer bus;

a multifunction device operably coupled to the computer bus, the multifunction device including a plurality of functions;

means for individually enabling or disabling a function of the plurality of functions of the multifunction device in response to a function configuration; and

a register space including a predefined header region and a device dependent region, the predefined header region including fields that uniquely identify the function and allow the function to be generically controlled, the device dependent region including an enable/disable byte register.

2. The computer system of claim 1 wherein:

the means for individually disabling further includes means for writing an indication to a location in the register space to disable a function of the plurality of functions.

3. The computer system of claim 2 further wherein the multifunction device further includes a plurality of register spaces, each register space associated with a function of the plurality, wherein the means for writing writes the indication to a location in a register space associated with the function to be disabled.

4. The computer system of claim 2 wherein:

the multifunction device further includes a plurality of register spaces, each register space associated with a function of the plurality; and

the means for writing further includes a means implemented in the multifunction device for, in response to an indication being written to one of the plurality of register spaces, writing an indication to a location in each of the other register spaces of the plurality of register spaces.

5. The computer system of claim 1 wherein the means for individually disabling further includes means for receiving a user indication to disable a function of a multifunction device.

6. The computer system of claim 1 wherein the computer bus substantially conforms to a PCI Local Bus standard and the multifunction device is a PCI compliant device.

7. A computer system comprising:

at least one system processor;

a computer bus, the at least one system processor operably coupled to the computer bus;

a multifunction device operably coupled to the computer bus, the multifunction device including a plurality of functions, the multifunction device including a register space including a predefined header region and a device dependent region, the predefined header region including fields that uniquely identify a function of the functions and allow the function to be generically controlled, the device dependent region including an enable/disable byte register; and

a memory for storing code whose execution writes an indication to a location in the register space to enable or disable a function of the plurality of functions in response to a function configuration.

8. The computer system according to claim 7 wherein:

the code is implemented in BIOS code.

9. The computer system of claim 7 wherein:

the multifunction device further includes a plurality of register spaces, each register space associated with a function of the plurality; and

execution of the code writes the indication to a register space associated with a first function of the plurality of functions.

10. The computer system of claim 9 wherein the first function is a function to be disabled.

11. The computer system of claim 9 wherein the multifunction device further includes a logic circuit which in response to a writing of the indication to the register associated with the first function, writes an indication to the other register spaces of the plurality of register spaces of the multifunction device.

12. The computer system of claim 7 wherein:

the multifunction device includes a first circuit; and

the multifunction device further includes a plurality of register spaces, each register space associated with a function of the plurality;

wherein in response to receiving from the computer bus a bus command addressed to a function, the first circuit reads the location in the register space associated with that function to determine if the function is disabled.

13. The computer system of claim 7 wherein the computer bus substantially conforms to a PCI Local Bus standard and the multifunction device is a PCI compliant device.

14. The computer system of claim 13 wherein:

the multifunction device further includes a plurality of configuration register spaces, each configuration register space associated with a function of the plurality;

wherein execution of the code writes the indication to a configuration register space associated with a function of the plurality of functions.

15. The computer system of claim 14 wherein the location is in a device dependent region of a configuration register space.

16. The computer system of claim 7 wherein the indication includes a bit for each function of the plurality representing whether the function is disabled.

17. A method for disabling a function of a multifunction device operably coupled to a computer bus comprising:

writing to a location in a register space of the multifunction device an indication to enable or disable a function in response to a function configuration, the register space including a predefined header region and a device dependent region, the predefined header region including fields that uniquely identify the function and allow the function to be generically controlled, the device dependent region including an enable/disable byte register;

generating a bus command on the computer bus addressed to the function; and

reading the indication in the location in the register space wherein the function is not responsive to the generated command in response to the reading that the function is disabled.

18. The method of claim 17 wherein each function of the multifunction device has an associated register space, wherein the location is in the register space associated with the first function.

19. The method of claim 17 wherein each function of the multifunction device has an associated register space and wherein the writing to a location in a register space further includes:

writing the indication to a register space associated with a first function of the plurality; and

writing the indication to a location in each of the register spaces associated with each of the functions other than the first function in response to the writing the indication to the register spaced associated with the first function.

20. The method of claim 19 wherein the first function is the function to be disabled.

21. The method of claim 17 further comprising:

receiving an indication to disable a second function of the multifunction device;

wherein the writing to the location in the register space further includes writing to the location an indication that the function and the second function are to be disabled.

22. The method of claim 17 further comprising:

receiving an indication to enable a disabled function of the plurality of functions;

determining that a second function of the plurality is enabled; and

writing to a register space associated with the second function an indication to enable the disabled function.

23. The method of claim 22 further comprising:

writing an indication that the disabled function is enabled to a register space associated with the disabled function in response to the writing to the register space associated with the second function an indication to enable the disabled function.

24. The method of claim 17 further wherein the indication further includes an indication of which functions of the plurality are disabled.

25. The method of claim 17 wherein the computer bus substantially conforms to a PCI Local Bus standard and the multifunction device is a PCI compliant device.

26. A computer system comprising:

at least one system processor;

a computer bus, the at least one system processor operably coupled to the computer bus;

a multifunction device located on the computer bus, the multifunction device including a plurality of functions, the multifunction device includes a register space, the multifunction device including a first circuit, wherein in response to a bus command addressed to a function of the multifunction device, the first circuit reads a location in the register space of the multifunction device to determine whether the function is configured as enabled or disabled and if enabled, then to be responsive to the bus command and if disabled, then to be non-responsive to the bus command; and

the register space including a predefined header region and a device dependent region, the predefined header region including fields that uniquely identify the function and allow the function to be generically controlled, the device dependent region including an enable/disable byte register.

27. The computer system of claim 26 wherein:

the multifunction device further includes a plurality of register spaces, each register space associated with a function of the plurality;

wherein the first circuit reads a location in the register space associated with the function to which the bus command is addressed.

28. The computer system of claim 27 wherein the multifunction device further includes a logic circuit which in response to a writing of an indication to a register space that a function is to be disabled, writes an indication to the other register spaces of the plurality of register spaces that the function is disabled.

29. The computer system of claim 26 wherein the computer bus substantially conforms to a PCI Local Bus standard and the multifunction device is a PCI compliant device.

30. The computer system of claim 29 wherein the location is a location in a configuration register space associated with the function to which the bus command is addressed.

31. The computer system of claim 30 wherein the location is in a device dependent region of a configuration register space.

32. The computer system of claim 26 wherein the first circuit is implemented in a bus interface circuit.