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Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle

  • US 6,647,506 B1
  • Filed: 11/30/1999
  • Issued: 11/11/2003
  • Est. Priority Date: 11/30/1999
  • Status: Expired due to Term
First Claim
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1. A synchronous bus system comprising:

  • a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices, the forward direction clock segment carrying a forward direction clock signal, the reverse direction clock segment carrying a reverse direction clock signal; and

    separate synchronization clock circuitry provided in each device, each synchronization clock circuitry operable to receive the forward direction clock signal and the reverse direction clock signal and to derive a universal synchronization clock signal which is synchronous throughout all devices, wherein each synchronization clock circuitry is operable to generate a flag signal for indicating whether a phase difference between the forward direction clock signal and the reverse direction clock signal is an even cycle phase difference or an odd cycle phase difference.

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