Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle

• US 6,647,506 B1
• Filed: 11/30/1999
• Issued: 11/11/2003
• Est. Priority Date: 11/30/1999
• Status: Expired due to Term

• Current Assignee: Integrated Memory Logic Limited (Maxlinear Incorporated)
• Original Assignee: Integrated Memory Logic Limited (Maxlinear Incorporated)
• Inventors: Tung, Chiayao S., Yang, Jeongsik, Park, Yong E., Chang, Shuen-Chin, Kim, Young Gon
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Wang, Albert
• Application Number:
  US09/452,274
• Time in Patent Office: 1,442 Days
• Field of Search: 327/292, 327/141, 375/356, 370/503, 711/167, 713/503
• US Class Current: 713/503
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew

Abstract

A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.

Claims

1. A synchronous bus system comprising:

a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices, the forward direction clock segment carrying a forward direction clock signal, the reverse direction clock segment carrying a reverse direction clock signal; and

separate synchronization clock circuitry provided in each device, each synchronization clock circuitry operable to receive the forward direction clock signal and the reverse direction clock signal and to derive a universal synchronization clock signal which is synchronous throughout all devices, wherein each synchronization clock circuitry is operable to generate a flag signal for indicating whether a phase difference between the forward direction clock signal and the reverse direction clock signal is an even cycle phase difference or an odd cycle phase difference.

2. The synchronous bus system of claim 1 wherein each synchronization clock circuitry is operable to identify a center of phase between the forward direction clock signal and the reverse direction clock signal.

3. The synchronous bus system of claim 1 wherein each synchronization clock circuitry is operable to identify an edge of the forward direction clock signal and an edge of the reverse direction clock signal.

4. The synchronous bus system of claim 1 wherein each synchronization clock circuitry is operable to select one of a plurality of clock signals, each clock signal having a different phase, for use as the universal synchronization clock signal.

5. The synchronous bus system of claim 1 wherein each synchronization clock circuitry comprises:

a phase selector circuit operable to select one of a plurality of clock signals, each clock signal having a different phase; and

a phase comparator operable to compare the selected clock signal against the reverse direction clock signal.

6. The synchronous bus system of claim 1 wherein the universal synchronization clock signal comprises:

a universal synchronization transmission clock signal for transmitting data at each device; and

a universal synchronization reception clock signal for receiving data at each device.

7. The synchronous bus system of claim 1 comprising separate skew correction circuitry in at least a portion of the devices, the skew correction circuitry operable to correct for skew between the universal synchronization clock signal and a data signal.

8. The synchronous bus system of claim 1 wherein each skew correction circuitry comprises:

a phase selector circuit for selecting one of a plurality of clock signals, each clock signal having a different phase; and

a phase comparator operable to compare the selected clock signal against the data signal.

9. The synchronous bus system of claim 7 wherein at least one device comprises control signal generation circuitry operable to generate skew correction data and to transmit the generated skew correction data to the other devices.

10. A synchronization clock circuitry comprising:

a multi-phase clock generator circuit operable to generate a plurality of clock signals, each clock signal having a different phase, the multi-phase clock generator circuit operable to receive a forward direction clock signal;

a controller operable to identify a difference in phase between the forward direction clock signal and a reverse direction clock signal using the single forward direction clock signal and the single reverse direction clock signal and no other forward or reverse direction clock signals even when a delay between the single forward direction clock signal and the single reverse direction clock signal is greater than one clock cycle, the controller operable to generate a control signal; and

a first phase selector circuit coupled to the multi-phase clock generator circuit and the controller, the first phase selector circuit operable to select one of the plurality of clock signals as a universal synchronization clock signal in response to the control signal.

11. The synchronization clock circuitry of claim 10 comprising a phase comparator operable to compare the reverse direction clock signal against one of the plurality of clock signals generated by the multi-phase clock generator circuit.

12. The synchronization clock circuitry of claim 10 comprising a second phase selector circuit coupled to the multi-phase clock generator circuit, the second phase selector circuit operable to select one of the plurality of clock signals for comparison against the reverse direction clock signal.

13. The synchronization clock circuitry of claim 10 comprising a phase selection latch circuit operable to store a value which designates one of the plurality of clock signals generated by the multi-phase clock generator circuit.

14. The synchronization clock circuitry of claim 13 wherein the controller is operable to output a signal for incrementing or decrementing the value stored in the phase selection latch circuit.

15. The synchronization clock circuitry of claim 10 wherein the controller comprises an even/odd cycle detector circuit operable to determine whether a phase difference between the forward direction clock signal and the reverse direction clock signal is an even cycle phase difference or an odd cycle phase difference.

16. A synchronous bus system comprising:

a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices, the forward direction clock segment carrying a forward direction clock signal, the reverse direction clock segment carrying a reverse direction clock signal, wherein a universal synchronization clock signal is derived at each device using the single forward direction clock signal and the single reverse direction clock signal and no other forward or reverse direction clock signals, wherein the universal synchronization clock signal is synchronous throughout all devices even when a delay between the forward direction clock signal and the reverse direction clock signal is greater than one clock cycle; and

separate skew correction circuitry in at least a portion of the devices, the skew correction circuitry operable to correct for skew between the universal synchronization clock signal and a data signal.

17. The synchronous bus system of claim 16 wherein at least one device comprises control signal generation circuitry operable to generate skew correction data and to transmit the generated skew correction data to the other devices.

18. The synchronous bus system of claim 16 wherein each skew correction circuitry comprises:

a phase selector circuit for selecting one of a plurality of clock signals, each clock signal having a different phase; and

a phase comparator operable to compare the selected clock signal against the data signal.

19. A synchronous bus system comprising:

a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices, the forward direction clock segment carrying a forward direction clock signal, the reverse direction clock segment carrying a reverse direction clock signal; and

synchronization means provided in each device, each synchronization means for deriving a universal synchronization clock signal using the single forward direction clock signal and the single reverse direction clock signal and no other forward or reverse direction clock signals, wherein the universal synchronization clock siagnal is synchronous throughout all devices even when a delay between the forward direction clock signal and the reverse direction clock signal is greater than one clock cycle.

20. The synchronous bus system of claim 19 wherein each synchronization means is operable to identify a center of phase between the forward direction clock signal and the reverse direction clock signal.

21. The synchronous bus system of claim 19 wherein each synchronization means is operable to generate a flag signal for indicating whether a phase difference between the forward direction clock signal and the reverse direction clock signal is an even cycle phase difference or an odd cycle phase difference.

22. The synchronous bus system of claim 19 wherein each synchronization means is operable to select one of a plurality of clock signals, each clock signal having a different phase, for use as the universal synchronization clock signal.

23. The synchronous bus system of claim 19 comprising separate skew correction means in at least a portion of the devices, the skew correction means for correcting for skew between the universal synchronization clock signal and a data signal.

24. A synchronous bus system comprising:

a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices, the forward direction clock segment carrying a forward direction clock signal, the reverse direction clock segment carrying a reverse direction clock signal; and

separate synchronization clock circuitry provided in each device, each synchronization clock circuitry operable to derive a universal synchronization clock signal using the single forward direction clock signal and the single reverse direction clock signal and no other forward or reverse direction clock signals, wherein the universal synchronization clock signal is synchronous throughout all devices even when a delay between the forward direction clock signal and the reverse direction clock signal is greater than one clock cycle.

25. The synchronous bus system of claim 24 wherein each synchronization clock circuitry is operable to identify a center of phase between the forward direction clock signal and the reverse direction clock signal.

26. The synchronous bus system of claim 24 wherein each synchronization clock circuitry is operable to identify an edge of the forward direction clock signal and an edge of the reverse direction clock signal.

27. The synchronous bus system of claim 24 wherein each synchronization clock circuitry is operable to select one of a plurality of clock signals, each clock signal having a different phase, for use as the universal synchronization clock signal.

28. The synchronous bus system of claim 24 wherein the universal synchronization clock signal comprises:

a universal synchronization transmission clock signal for transmitting data at each device; and

a universal synchronization reception clock signal for receiving data at each device.

29. The synchronous bus system of claim 24 comprising separate skew correction circuitry in at least a portion of the devices, the skew correction circuitry operable to correct for skew between the universal synchronization clock signal and a data signal.