Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands

• US 6,649,477 B2
• Filed: 10/04/2001
• Issued: 11/18/2003
• Est. Priority Date: 10/04/2001
• Status: Active Grant

• Current Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Blanchard, Richard A., Guillot, Jean-Michel
• Primary Examiner(s): Cao, Phat X.
• Assistant Examiner(s): Le, Thao X.
• Application Number:
  US09/970,758
• Publication Number:
  US 20030068854A1
• Time in Patent Office: 775 Days
• Field of Search: 438/212, 438/270, 438/493, 438/211, 438/259, 438/221, 438/589, 438/284, 438/286, 438/101, 438/931, 438/268, 438/296, 438/298, 438/433-434, 257/328-330
• US Class Current: 438/268
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region. A filler material is deposited in the terraced trench to substantially fill the trench, thus completing the voltage sustaining region. At least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween.

Claims

1. A method of forming a power semiconductor device comprising the steps of:

A. providing a substrate of a first conductivity type;

B. forming a voltage sustaining region on said substrate by;

I. depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type;

II. forming at least one terraced trench in said epitaxial layer, said terraced trench having a plurality of portions that differ in width to define at least one annular ledge therebetween;

III. depositing a barrier material along the walls and bottom of said trench, the barrier material having a substantially uniform thickness;

IV. implanting a dopant of a second conductivity type through the barrier material lining said at least one annular ledge and said trench bottom and into adjacent portions of the epitaxial layer;

V. diffusing said dopant to form at least one annular doped region in said epitaxial layer and at least one other region located below said annular doped region in said epitaxial layer;

VI. depositing a filler material in said terraced trench to substantially fill said terraced trench; and

C. forming over said voltage sustaining region at least one region of said second conductivity type to define a junction therebetween,

wherein the substantially uniform thickness of the barrier material prevents implanted dopant from penetrating the walls of said trench, but allows implanted dopant to penetrate through a portion of the barrier material lining said at least one annular ledge and said trench bottom.

2. The method of claim 1 wherein the step of forming said at least one terraced trench includes the steps of successively etching the plurality of portions of the terraced trench beginning with a largest width portion and ending with a smallest width portion.

3. The method of claim 2 wherein said smallest width portion is located at a depth in said epitaxial layer such that it is closer to the substrate than the largest width portion.

4. The method of claim 1 wherein said plurality of portions of the terraced trench are coaxially located with respect to one another.

5. The method of claim 1 wherein said plurality of portions of the terraced trench includes at least three portions that differ in width from one another to define at least two annular ledges and said at least one annular doped region includes at least two annular doped regions.

6. The method of claim 4 wherein said plurality of portions of the terraced trench includes at least three portions that differ in width from one another to define at least two annular ledges and said at least one annular doped region includes at least two annular doped regions.

7. The method of claim 6 wherein the step of forming at least one terraced trench includes the steps of successively etching said at least three portions of the terraced trench beginning with a largest width portion and ending with a smallest width portion.

8. The method of claim 7 wherein said smallest width portion is located at a depth in said epitaxial layer such that it is closer to the substrate than said largest width portion.

9. The method of claim 1 wherein step (C) further includes the steps of:

forming a gate conductor above a gate dielectric region;

forming first and second body regions in the epitaxial layer to define a drift region therebetween, said body regions having a second conductivity type;

forming first and second source regions of the first conductivity type in the first and second body regions, respectively.

10. The method of claim 1 wherein said barrier material is an oxide material.

11. The method of claim 10 wherein said oxide material is silicon dioxide.

12. The method of claim 1 wherein said dopant is boron.

13. The method of claim 9 wherein said body regions include deep body regions.

14. The method of claim 1, wherein said terraced trench is formed by providing a masking layer defining at least a first of said plurality of portions and etching said first portion defined by the masking layer.

15. The method of claim 14 further comprising the step of depositing an oxide layer of prescribed thickness along the walls of said first portion of the terraced trench.

16. The method of claim 15 wherein said oxide layer serves as a second masking layer and further comprising the step of etching a second portion of the terraced trench defined by the second masking layer through a bottom surface of the first portion of the terraced trench.

17. The method of claim 16 wherein said prescribed thickness of the oxide layer is selected so that a surface area of the annular ledge and the non-annular region are substantially equal to one another.

18. The method of claim 9, wherein said body region is formed by implanting and diffusing a dopant into the substrate.

19. The method of claim 1 wherein said power semiconductor device is selected from the group consisting of a vertical DMOS, V-groove DMO, and a trench DMOS MOSFET, an IGBT, and a bipolar transistor.

20. A method of forming a power semiconductor device comprising the steps of:

A. providing a substrate of a first conductivity type;

B. forming a voltage sustaining region on said substrate by;

I. depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type;

II. forming at least one terraced wench in said epitaxial layer, said terraced trench having a plurality of portions that differ in width to define at least one annular ledge therebetween

III. depositing a barrier material along the walls and bottom of said french;

IV. implanting a dopant of a second conductivity type through the barrier material lining said at least one annular ledge and said wench bottom and into adjacent portions of the epitaxial layer;

V. diffusing said dopant to form at least one annular doped region in said epitaxial layer and at least one other region located below said annular doped region in said epitaxial layer;

VI. depositing a filler material in said terraced trench to substantially fill said terraced trench; and

C. forming over said voltage sustaining region at least one region of said second conductivity type to define a junction therebetween,

wherein said epitaxial layer has a given thickness and further comprising the step of etching a first portion of the terraced trench by an amount substantially equal to 1/(x+1) of said given thickness, where x is equal to or greater than a prescribed number of annular doped regions to be formed in the voltage sustaining region.

21. A method of forming a power semiconductor device comprising the steps of:

A. providing a substrate of a first conductivity type;

B. forming a voltage sustaining region on said substrate by;

I. depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type;

II. forming at least one terraced trench in said epitaxial layer, said terraced trench having a plurality of portions that differ in width to define at least one annular ledge therebetween;

III. depositing a barrier material along the walls and bottom of said trench;

IV. implanting a dopant of a second conductivity type through the barrier material Lining said at least one annular ledge and said trench bottom and into adjacent portions of the epitaxial layer;

V. diffusing said dopant to form at least one annular doped region in said epitaxial layer and at least one other region located below said annular doped region in said epitaxial layer;

VI. depositing a filler material in said terraced trench to substantially fill said terraced trench; and

C. forming over said voltage sustaining region at least one region of said second conductivity type to define a junction therebetween,

wherein said material filling the trench is a dielectric material.

22. The method of claim 21 wherein said dielectric material is silicon dioxide.

23. The method of claim 21 wherein said dielectric material is silicon nitride.

24. A method of forming a power semiconductor device comprising the steps of:

A. providing a substrate of a first conductivity type;

B. Corning a voltage sustaining region on said substrate by;

I. depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type;

II. forming at least one terraced trench in said epitaxial layer, said terraced trench having a plurality of portions that differ in width to define at least one annular ledge therebetween;

III. growing a barrier material along the walls and bottom of said trench, the barrier material having a substantially uniform thickness;

IV. implanting a dopant of a second conductivity type through the barrier material lining said at least one annular ledge and said trench bottom and into adjacent portions of the epitaxial layer;

V. diffusing said dopant to form at least one annular doped region in said epitaxial layer and at least one other region located below said annular doped region in said epitaxial layer;

VI. depositing a filler material in said terraced trench to substantially fill said terraced trench; and

C. forming over said voltage sustaining region at least one region of said second conductivity type to define a junction therebetween,

wherein the substantially uniform thickness of the barrier material prevents implanted dopant from penetrating the walls of said trench, but allows implanted dopant to penetrate through a portion of the barrier material lining said at least one annular ledge and said trench bottom.