Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

• US 6,649,972 B2
• Filed: 04/15/2002
• Issued: 11/18/2003
• Est. Priority Date: 08/01/1997
• Status: Expired due to Term

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US10/122,078
• Publication Number:
  US 20030011020A1
• Time in Patent Office: 582 Days
• Field of Search: 257/314, 257/315, 257/316, 257/324, 257/325, 257/390
• US Class Current: 257/324
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation

Abstract

A programmable, read only memory device includes two diffusion areas in a substrate and a channel formed therebetween, an oxide-nitride-oxide (ONO) layer comprising a first oxide layer overlaid by a nitride layer overlaid by a second oxide layer, the nitride layer having a thickness of 100 Angstroms or less and having two charge storage areas therein, each having a narrow width so that, during a read operation, current flows under the charge storage area not being read and a gate.

Claims

1. A programmable, read only memory device comprising:

two diffusion areas in a substrate and a channel formed therebetween;

an oxide-nitride-oxide (ONO) layer comprising a first oxide layer overlaid by a nitride layer overlaid by a second oxide layer, the nitride layer having a thickness of 100 Angstroms or less and having two charge storage areas therein, each having a narrow width so that, during a read operation, current flows under the charge storage area not being read; and

a gate.

2. A device according to claim 1 wherein the widths of said charge storage areas enables the stored charge to be erased.

3. A device according to claim 1 wherein each said charge storage area is adapted to be programmed with a voltage on the diffusion area near the charge storage area being programmed which is substantially lower than a voltage on said gate.

4. A device according to claim 1 wherein each charge storage area is adapted to be programmed and erased multiple times.

5. A programmable, read only memory device comprising:

two diffusion areas in a substrate and a channel formed therebetween;

a non-conducting charge storage layer having two charge storage areas therein, each near one of said diffusion areas; and

a gate,

wherein each said charge storage area is adapted to be read in a direction opposite to that in which it was programmed, and

wherein each said charge storage area is adapted to be programmed with a voltage on the diffusion area near said charge storage area which is substantially lower than a voltage on said gate.

6. A device according to claim 5 wherein said non-conducting charge storage layer comprises a first oxide layer overlaid by a nitride layer overlaid by a second oxide layer, the nitride and first and second oxide layers having a thickness of 100 Angstroms or less.