Apparatus and method for forming a battery in an integrated circuit
First Claim
1. An electrochemical structure within an integrated circuit, comprising:
- a semiconductor wafer;
a layer of electronic devices on the semiconductor wafer, wherein the layer of electronic devices includes at least one electronic device;
N wiring levels within an interconnect structure of the integrated circuit, wherein the N wiring levels are disposed on the layer of electronic devices, wherein N is at least 1, wherein the N wiring levels are denoted as wiring level 1, wiring level 2, . . . , wiring level N, and wherein the N wiring levels include a first conductive metallization and a second conductive metallization; and
at least one battery within the wiring levels I through K, wherein I is selected from the group consisting of 1, 2, . . . , and N, wherein K is selected from the group consisting of I, I+1, . . . , and N, wherein the first conductive metallization conductively couples a first electrode of the at least one battery to the at least one electronic device, wherein the second conductive metallization conductively couples a second electrode of the battery to the at least one electronic device, wherein the first and second conductive metallizations are totally external to the interior of the at least one battery, and wherein said electrodes are external to the first and second conductive metallizations.
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Accused Products
Abstract
A method and structure that provides a battery within an integrated circuit for providing voltage to low-current electronic devices that exist within the integrated circuit. The method includes Front-End-Of-Line (FEOL) processing for generating a layer of electronic devices on a semiconductor wafer, followed by Back-End-Of-Line (BEOL) integration for wires connecting the electronic devices together to form completed electrical circuits of the integrated circuit. The BEOL integration includes forming a multilayered structure of wiring levels on the layer of electronic devices. Each wiring level includes conductive metallization (e.g., metal-plated vias, conductive wiring lines, etc.) embedded in insulative material. The battery is formed during BEOL integration within one or more wiring levels, and the conductive metallization conductively couples positive and negative terminals of the battery to the electronic devices. The battery may have several different topologies relative to the structural and geometrical relationships among the battery electrodes and electrolyte. Multiple batteries may be formed within one or more wiring levels, and may be conductively coupled to the electronic devices. The multiple batteries may be connected in series or in parallel.
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Citations
14 Claims
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1. An electrochemical structure within an integrated circuit, comprising:
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a semiconductor wafer;
a layer of electronic devices on the semiconductor wafer, wherein the layer of electronic devices includes at least one electronic device;
N wiring levels within an interconnect structure of the integrated circuit, wherein the N wiring levels are disposed on the layer of electronic devices, wherein N is at least 1, wherein the N wiring levels are denoted as wiring level 1, wiring level 2, . . . , wiring level N, and wherein the N wiring levels include a first conductive metallization and a second conductive metallization; and
at least one battery within the wiring levels I through K, wherein I is selected from the group consisting of 1, 2, . . . , and N, wherein K is selected from the group consisting of I, I+1, . . . , and N, wherein the first conductive metallization conductively couples a first electrode of the at least one battery to the at least one electronic device, wherein the second conductive metallization conductively couples a second electrode of the battery to the at least one electronic device, wherein the first and second conductive metallizations are totally external to the interior of the at least one battery, and wherein said electrodes are external to the first and second conductive metallizations. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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Specification