Stackable ceramic fbga for high thermal applications

• US 6,650,007 B2
• Filed: 08/08/2001
• Issued: 11/18/2003
• Est. Priority Date: 06/30/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Corisis, David J., Kinsman, Larry D., Moden, Walter L., Mess, Leonard E.
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): VU, QUANG D
• Application Number:
  US09/924,635
• Publication Number:
  US 20010048152A1
• Time in Patent Office: 832 Days
• Field of Search: 257/685, 257/686, 257/687, 257/725, 257/730, 257/731, 257/732, 257/733, 257/737, 257/777, 438/109, 438/613
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15173 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1627 : stacked type assemblies, e.g. stacked multi-cavities
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

An apparatus package for high-temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor devices.

Claims

1. A stackable assembly comprising:

a first carrier having a cavity therein, an upper surface, a lower surface, a connection pad on the upper surface, a connection pad on the lower surface, a first circuit connecting the connection pad on the upper surface to the connection pad on the lower surface, and a second circuit located in a portion of the cavity connected to the connection pad on the upper surface and the connection pad on the lower surface;

a semiconductor device having an active surface having a bond pad thereon, the semiconductor device located within the cavity of the first carrier;

a first connector between the second circuit located in the portion of the cavity of the first carrier and the bond pad on the active surface of the semiconductor device; and

encapsulant material filling the portion of the cavity in the first carrier.

2. The stackable assembly of claim 1, further comprising:

a substrate having an upper surface, a lower surface, and a circuit on the upper surface thereof; and

at least one second connector connected to the connection pad on the lower surface of the first carrier and a circuit on the upper surface of the substrate.

3. The stackable assembly of claim 1, wherein the first carrier includes a fin on a portion thereof.

4. The stackable assembly of claim 1, further comprising:

a second carrier oriented with respect to the first carrier and positioned the same direction as the first carrier and further having a cavity therein, an upper surface, a lower surface, a connection pad on the upper surface thereof, a connection pad on the lower surface thereof, a first circuit connecting the connection pad on the upper surface thereof to the connection pad on the lower surface thereof, and a second circuit located in a portion of the cavity therein connected to the connection pad on the upper surface thereof and the connection pad on the lower surface thereof,

a semiconductor device having an active surface having a bond pad thereon, the semiconductor device located within the cavity of the second carrier;

a first connector between the second circuit located in the portion of the cavity of the second carrier and the bond pad on the active surface of the semiconductor device located in the second carrier; and

encapsulant material filling a portion of the cavity in the second carrier.

5. The stackable assembly of claim 1, wherein the first carrier includes a first frustoconical surface on a portion thereof, a second frustoconical surface on another portion thereof, and a lip on a portion of a bottom surface thereof.

6. A stackable semiconductor device assembly comprising:

a first carrier having a cavity therein, an upper surface, a lower surface, a plurality of connection pads on the upper surface, a plurality of connection pads on the lower surface, a plurality of first circuits connecting the plurality of connection pads on the upper surface to the plurality of connection pads on the lower surface, and a plurality of second circuits located in a portion of the cavity connected to the plurality of connection pads on the upper surface and the plurality of connection pads on the lower surface;

a semiconductor device having an active surface having a plurality of bond pads thereon, the semiconductor device located within the cavity of the first carrier;

a first connector between at least one second circuit of the plurality of second circuits located in the portion of the cavity of the first carrier and at least one bond pad of the plurality of bond pads on the active surface of the semiconductor device; and

encapsulant material filling the portion of the cavity in the first carrier.

7. The stackable semiconductor device assembly of claim 6, further comprising:

a substrate having an upper surface, a lower surface, and at least one third circuit on the upper surface thereof; and

at least one second connector connected to at least one connection pad of the plurality of connection pads on the lower surface of the first carrier and the at least one third circuit on the upper surface of the substrate.

8. The stackable semiconductor device assembly of claim 6, wherein the first carrier includes at least one fin on a portion thereof.

9. The stackable semiconductor device assembly of claim 6, further comprising:

a second carrier oriented with respect to the first carrier and positioned in a same direction as the first carrier and further having a cavity therein, an upper surface, a lower surface, a plurality of connection pads on the upper surface thereof, a plurality of connection pads on the lower surface thereof, a plurality of first circuits connecting the plurality of connection pads on the upper surface thereof to the plurality of connection pads on the lower surface thereof, and a plurality of second circuits located in a portion of the cavity connected to the plurality of connection pads on the upper surface thereof and the plurality of connection pads on the lower surface thereof;

a semiconductor device having an active surface having a plurality of bond pads thereon, the semiconductor device located within the cavity of the second carrier;

a first connector between at least one second circuit of the plurality of second circuits located in a portion of the cavity of the second carrier and at least one bond pad of the plurality of bond pads on the active surface of the semiconductor device located within the cavity of the second carrier; and

encapsulant material filling the portion of the cavity in the second carrier.

10. The stackable semiconductor device assembly of claim 6, wherein the first carrier includes a first frustoconical surface on a portion thereof, a second frustoconical surface on another portion thereof, and a lip on a portion of a bottom surface thereof.

11. A stackable assembly comprising:

a substrate having an upper surface, a lower surface, and a plurality of first circuits on the upper surface thereof,

a first carrier having a cavity therein, an upper surface, a lower surface, a plurality of connection pads on the upper surface thereof, a plurality of connection pads on the lower surface thereof, at least one second circuit of a plurality of second circuits connecting at least one connection pad of the plurality of connection pads on the upper surface to at least one connection pad of the plurality of connection pads on the lower surface, and a plurality of second circuits located in a portion of the cavity connected to the plurality of connection pads on the upper surface and the plurality of connection pads on the lower surface;

a semiconductor device having an active surface having a plurality of bond pads thereon, the semiconductor device located within the cavity of the first carrier;

a first connector between at least one third circuit of the plurality of third circuits located in the portion of the cavity of the first carrier and at least one bond pad of the plurality of bond pads on the active surface of the semiconductor device;

encapsulant material filling the portion of the cavity in the first carrier; and

at least one second connector connected to the at least one connection pad of the plurality of connection pads on the lower surface of the first carrier and at least one first circuit of the plurality of first circuits on the upper surface of the substrate.

12. The stackable assembly of claim 11, wherein the first carrier includes at least one fin on a portion thereof.

13. The stackable assembly of claim 11, further comprising:

a second carrier oriented with respect to the first carrier and positioned in a same direction as the first carrier and further having a cavity therein, an upper surface, a lower surface, a plurality of connection pads on the upper surface thereof, a plurality of connection pads on the lower surface thereof, a first circuit connecting at least one connection pad of the plurality of connection pads on the upper surface thereof to at least one connection pad of the plurality of connection pads on the lower surface thereof, and at least one second circuit of a plurality of second circuits located in a portion of the cavity thereof connected to at least one connection pad of the plurality of connection pads on the upper surface thereof and at least one connection pad of the plurality of connection pads on the lower surface thereof;

a semiconductor device having an active surface having a plurality of bond pads thereon, the semiconductor device located within the cavity of the second carrier;

a first connector between the at least one second circuit of the plurality of second circuits located in the portion of the cavity of the second carrier and at least one bond pad of the plurality of bond pads on the active surface of the semiconductor device located within the cavity of the second carrier; and

encapsulant material filling a portion of the cavity in the second carrier.

14. The stackable assembly of claim 11, wherein the first carrier includes a first frustoconical surface on a portion thereof, a second frustoconical surface on another portion thereof, and a lip on a portion of a bottom surface thereof.

15. A stackable semiconductor device assembly comprising:

a substrate having an upper surface, a lower surface, and at least one circuit on the upper surface thereof;

a first carrier having a cavity therein, an upper surface, a lower surface, at least one connection pad on the upper surface thereof, at least one connection pad on the lower surface thereof, at least one first circuit connecting the at least one connection pad on the upper surface thereof to the at least one connection pad on the lower surface thereof, at least one second circuit located in a portion of the cavity connected to the at least one connection pad on the upper surface and the at least one connection pad on the lower surface thereof;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the first carrier;

a first connector between the at least one second circuit located in the portion of the cavity of the first carrier and the at least one bond pad on the active surface of the semiconductor device;

encapsulant material filling a portion of the cavity in the first carrier; and

at least one second connector connected to the at least one connection pad on the lower surface of the first carrier and the at least one circuit on the upper surface of the substrate.

16. The stackable semiconductor device assembly of claim 15, wherein the first carrier includes at least one fin on a portion thereof.

17. The stackable semiconductor device assembly of claim 15, further comprising:

a second carrier oriented with respect to the first carrier and positioned in a same direction as the first carrier and further having a cavity therein, an upper surface, a lower surface, a plurality of connection pads on the upper surface thereof, a plurality of connection pads on the lower surface thereof, a first circuit connecting at least one connection pad of the plurality of connection pads on the upper surface thereof to at least one connection pad of the plurality of connection pads on the lower surface thereof, and at least one second circuit located in a portion of the cavity connected to the at least one connection pad of the plurality of connection pads on the upper surface thereof and the at least one connection pad of the plurality of connection pads on the lower surface thereof;

a semiconductor device having an active surface having a plurality of bond pads thereon, the semiconductor device located within the cavity of the second carrier;

a first connector between the at least one second circuit located in the portion of the cavity of the second carrier and at least one bond pad of the plurality of bond pads on the active surface of the semiconductor device located within the cavity of the second carrier; and

encapsulant material filling a portion of the cavity in the second carrier.

18. The stackable semiconductor device assembly of claim 15, wherein the first carrier includes a first frustoconical surface on a portion thereof, a second frustoconical surface on another portion thereof, and a lip on a portion of a bottom surface thereof.

19. A stackable assembly comprising:

a substrate having an upper surface, a lower surface, and a plurality of circuits on the upper surface thereof;

a first carrier having a cavity therein, an upper surface, a lower surface, a plurality of connection pads on the upper surface thereof, a plurality of connection pads on the lower surface thereof, at least one first circuit of a plurality of first circuits connecting at least one connection pad of the plurality of connection pads on the upper surface to at least one connection pad of the plurality of connection pads on the lower surface, and at least one second circuit of a plurality of second circuits located in a portion of the cavity connected to the at least one connection pad of the plurality of connection pads on the upper surface and the at least one connection pad of the plurality of connection pads on the lower surface;

a first semiconductor device having an active surface having a plurality of bond pads thereon, the first semiconductor device located within the cavity of the first carrier;

a first connector between the at least one second circuit of the plurality of second circuits located in the portion of the cavity of the first carrier and at least one bond pad of the plurality of bond pads on the active surface of the first semiconductor device;

encapsulant material filling the portion of the cavity in the first carrier;

at least one second connector connected to the at least one connection pad of the plurality of connection pads on the lower surface of the first carrier and at least one circuit of the plurality of circuits on the upper surface of the substrate;

a second carrier oriented with respect to the first carrier and positioned the same direction as the first carrier and further having a cavity therein, an upper surface, a lower surface, a plurality of connection pads on the upper surface thereof, a plurality of connection pads on the lower surface thereof, at least one first circuit of a plurality of first circuits connecting at least one connection pad of the plurality of connection pads on the upper surface thereof to at least one connection pad of the plurality of connection pads on the lower surface thereof, and at least one second circuit of a plurality of second circuits located in a portion of the cavity therein connected to the at least one connection pad of the plurality of connection pads on the upper surface thereof and the at least one connection pad of the plurality of connection pads on the lower surface thereof;

a second semiconductor device having an active surface having a plurality of bond pads thereon, the second semiconductor device located within the cavity of the second carrier;

a third connector between the at least one second circuit of the plurality of second circuits located in the portion of the cavity of the second carrier and at least one bond pad of the plurality of bond pads on the active surface of the second semiconductor device;

encapsulant material filling a portion of the cavity in the second carrier;

at least one second connector connected to the at least one connection pad of the plurality of connection pads on the lower surface of the second carrier and at least one circuit of the plurality of circuits on the lower surface of the substrate.

20. The stackable assembly of claim 19, wherein the first carrier includes at least one fin on a portion thereof.

21. The stackable assembly of claim 19, further comprising:

a third carrier oriented with respect to the first carrier and positioned in a same direction as the first carrier and further having a cavity therein, an upper surface, a lower surface, a plurality of connection pads on the upper surface thereof, a plurality of connection pads on the lower surface thereof, a first circuit of a plurality of first circuits connecting at least one connection pad on the upper surface thereof to at least one connection pad on the lower surface thereof, and at least one second circuit of a plurality of second circuits located in a portion of the cavity thereof connected to the at least one connection pad on the upper surface thereof and the at least one connection pad on the lower surface thereof;

a third semiconductor device having an active surface having a plurality of bond pads thereon, the third semiconductor device located within the cavity of the third carrier;

a fourth connector between the at least one second circuit of the plurality of second circuits located in the portion of the cavity of the third carrier and at least one bond pad of the plurality of bond pads on the active surface of the third semiconductor device; and

encapsulant material filling the portion of the cavity in the third carrier.

22. The stackable assembly of claim 19, wherein the first carrier includes a first frustoconical surface on a portion thereof, a second frustoconical surface on another portion thereof, and a lip on a portion of a bottom surface thereof.