Semiconductor memory device, and method for testing the same

• US 6,650,581 B2
• Filed: 04/23/2002
• Issued: 11/18/2003
• Est. Priority Date: 06/29/2001
• Status: Expired due to Fees

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kim, Si Hong, Hong, Sang Hoon
• Primary Examiner(s): PHUNG, ANH K
• Application Number:
  US10/128,393
• Publication Number:
  US 20030002367A1
• Time in Patent Office: 574 Days
• Field of Search: 365/201, 365/200, 365/189.07, 365/194, 365/191
• US Class Current: 365/201
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing

Abstract

A semiconductor memory device and a method for testing the same which optimizes operation conditions by detecting a test cell that may easily fail in a test among the memory cells passing a burn-in test, and detecting the worst operation conditions by performing the test on the test cell. The device and method reduce power consumption in a refresh or active operation. According to the device and method set forth, a test unit tests a test cell, controls operation conditions of the semiconductor memory device according to the test result, and outputs the operation conditions. A driving unit drives the semiconductor memory device using the operation conditions controlled by the test unit.

Claims

1. A semiconductor memory device comprising:

a memory cell array comprising a test cell determined as a worst one among the memory cells passing a first test;

a test unit for performing a second test on the test cell in predetermined operation conditions, repeatedly performing the second test after adjusting the operation conditions of the test cell according to the result of the second test and finally outputting the final operation conditions; and

a driving unit for driving the memory cell array by using the final operation conditions from the test unit.

2. The device according to claim 1, wherein the test unit comprises:

a delay for reading data stored in the test cell, and delaying the data for a predetermined time;

a data comparator for comparing the delayed data with a test data, and outputting the comparison result;

an operation condition controller for adjusting the operation conditions according to the comparison result from the data comparator; and

a test controller for controlling the second test in which the test data is stored and read from/to the test cell in the adjusted operation conditions.

3. The device according to claim 2, wherein the delay comprises a plurality of unit delays controlled according to a plurality of control signals, for adjusting a delay rate.

4. The device according to claim 2, wherein the data comparator comprises:

a first latch for latching a data delayed by the delay, and outputting the latched data;

a second latch for latching the test data, and outputting the latched data; and

a comparator for comparing data outputted from the first and second latches, and outputting a comparison result signal.

5. The device according to claim 4, wherein the first latch is synchronized with a clock signal pursuant to a test operation period, for outputting the latched data.

6. The device according to claim 4, wherein the second latch is synchronized with a clock signal in accordance with a time of enabling a word line connected to the test cell to write the test data to be stored in the test cell, for outputting the latched data.

7. The device according to claim 2, wherein the operation condition controller controls a refresh period by adjusting an operation parameter according to the comparison result of the data comparator.

8. The device according to claim 2, wherein the operation condition controller controls an enable speed of a sense amplifier by adjusting a skew of a sense amplifier enable signal according to the output signal from the data comparator.

9. The device according to claim 2, wherein the operation condition controller controls a refresh period by adjusting an operation parameter according to the output signal from the data comparator, and controls an enable speed of a sense amplifier by adjusting a skew of a sense amplifier enable signal according to the output signal from the data comparator.

10. The device according to claim 2, wherein the test controller memorizes an address of the test cell.

11. A method for testing a semiconductor memory device, comprising:

detecting a test cell which may easily fail among the cells passing a first test, repairing the test cell, and memorizing an address of the test cell;

a test step for performing a second test on the test cell in predetermined operation conditions by using the address of the test cell;

returning to the test step after adjusting the operation conditions, when the test cell passes the second test; and

providing the operation conditions used in the second test as driving conditions of a memory cell array, when the test cell fails in the second test.

12. The method according to claim 11, further comprising comparing data obtained by delaying a data stored in the test cell for a predetermined time with test data.

13. The method according to claim 11, wherein the operation condition is a refresh period.

14. The method according to claim 13, wherein the second test is automatically performed when a refresh operation is performed.

15. The method according to claim 11, wherein the operation condition is an enable speed of a sense amplifier.

16. The method according to claim 15, further comprising confirming of the input of a test command, and performs the second test when the test command is inputted.

17. The method according to claim 11, wherein the operation condition is a refresh period and an enable speed of a sense amplifier.