Secure fast packet switch having improved memory utilization

• US 6,650,639 B2
• Filed: 05/24/2000
• Issued: 11/18/2003
• Est. Priority Date: 09/27/1996
• Status: Expired due to Term

• Current Assignee: Extreme Networks, Inc.
• Original Assignee: Enterasys Networks Incorporated (Extreme Networks, Inc.)
• Inventors: Grimes, Andrew, Doherty, James P.
• Primary Examiner(s): NGUYEN, STEVEN H D
• Application Number:
  US09/578,143
• Publication Number:
  US 20030048779A1
• Time in Patent Office: 1,273 Days
• Field of Search: 370/254-256, 370/252-253, 370/379-389, 370/392, 370/394, 370/395-396, 370/397-402, 370/409, 370/419, 370/422, 370/423, 370/424, 370/428, 370/395.31, 370/395.32, 370/216, 370/221, 707/1, 707/3, 707/6, 707/100, 707/104, 707/509, 707/395.31, 707/395.32, 709/238, 709/242, 709/395.31, 709/395.32, 711/46, 711/221, 711/395.31, 711/216
• US Class Current: 370/389
• CPC Class Codes: H04L 41/0213 Standardised network management protocols, e.g. simple network management protocol [SNMP]
• CPC Class Codes: H04L 41/046 comprising network management agents or mobile agents therefor
• CPC Class Codes: H04L 43/50 Testing arrangements
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/742 Route cache; Operation thereof
• CPC Class Codes: H04L 63/0236 Filtering by address, protocol, port number or service, e.g. IP-address or URL
• CPC Class Codes: H04L 63/0272 Virtual private networks

Abstract

In a secure fast packet switch having a plurality of input ports and a plurality of output ports, a method of determining which port in the plurality of output ports data that is received on one input port in the plurality of input ports is to be sent to, the method including the steps of determining a physical layer address of a sending node, determining a physical layer address of a receiving node, determining an input port in the plurality of input ports that the data was received on, determining if the physical layer address of the sending node and the physical layer address of the receiving node are an allowed combination, determining the magnitude of the node identification number of the sending node, determining the magnitude of the node identification number of the receiving node, obtaining outbound port information from a first predetermined location in a data structure stored in a memory if the node identification number of the sending node is greater than the node identification number of the receiving node, and obtaining outbound port information from a second predetermined location in the data structure stored in the memory if the node identification number of the sending node is less than the node identification number of the receiving node. Circuitry that carries out the method is also described along with an exemplary data structure.

Claims

1. A switch, comprising:

a memory for storing data;

a single entry stored in the memory for each pair of nodes between which a communication is permitted, each pair of nodes including a first node and a second node each having a physical layer address, the entry being accessible based upon the physical layer addresses of the first and second nodes, the entry comprising;

a first field in a first predetermined location in the entry, the first field identifying a first input port in the switch when the first node is a source of the communication;

a second field in a second predetermined location in the entry, the second field identifying a second input port in the switch when the first node is a destination of the communication;

a third field in a third predetermined location in the entry, the third field identifying a first output port in the switch when the first node is the source of the communication; and

a fourth field in a fourth predetermined location in the entry, the fourth field identifying a second output port in the switch when the first node is the destination of the communication.

2. A switch, comprising:

a memory for storing data; and

a single entry stored in the memory for each pair of nodes between which a communication is permitted, each pair of nodes including a first node and a second node each having a physical layer address, the entry being accessible based upon the physical layer addresses of the first and second nodes, the entry including first and second fields stored in corresponding first and second predetermined locations in the entry;

wherein the first predetermined location at which the first field is stored identifies a first output port of the switch to which the communication is sent when the first node is the source of the communication and wherein the second predetermined location at which the second field is stored identifies a second output port of the switch to which the communication is sent when the first node is a destination of the communication.

3. The switch of claim 2, wherein the entry further includes:

third and fourth fields stored in corresponding third and fourth predetermined locations in the entry;

wherein the third predetermined location at which the third field is stored identifies a first input port of the switch on which the communication is received when the first node is the source of the communication and wherein the fourth predetermined location at which the fourth field is stored identifies a second input port of the switch on which the communication is received when the first node is the destination of the communication.