Phase locked loop with numerically controlled oscillator divider in feedback loop

• US 6,650,721 B1
• Filed: 08/05/1999
• Issued: 11/18/2003
• Est. Priority Date: 08/05/1999
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Janesch, Stephen T., Stevenson, Carl R.
• Primary Examiner(s): PHU, PHUONG M
• Application Number:
  US09/368,583
• Time in Patent Office: 1,566 Days
• Field of Search: 375/376, 375/327, 375/375, 375/374, 375/373, 327/147, 327/150, 327/156, 327/159, 331/1.R, 331/25, 331/34, 331/1.A, 329/307-309, 329/325, 329/326, 329/360, 332/127, 332/128
• US Class Current: 375/376
• CPC Class Codes: H03C 3/095 applying frequency modulation to the loop in front of the voltage controlled oscillator
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/1806 the frequency divider comprising a phase accumulator generating the frequency divided signal

Abstract

A digital phase locked loop (PLL) frequency synthesizer includes a 1-bit numerically controlled oscillator (NCO) to negate the requirement that a VCO frequency be an integer multiple of its reference frequency. Thus, in accordance with the principles of the present invention, a direct digital synthesizer (DDS) or numerically controlled oscillator (NCO) is used to form a frequency divider in a feedback path of a PLL. Thus, a synthesizer with fine frequency control and very fast settling time is disclosed. The conventional integer-ratio relationship between the reference frequency f_REF and the synthesized output frequency signal f_VCO is overcome by replacement of a conventional VCO divider in a feedback path of a digital PLL with a 1-bit NCO. This allows the reference frequency f_REF to be greater than the channel spacing, i.e., the channel spacing can be smaller than the reference frequency f_REF. Thus, a much quicker settling time and improved VCO phase noise are provided, either of which results in a significant improvement in the performance of virtually any communications system.

Claims

1. A digital phase locked loop, comprising:

a phase detector receiving at a first input a representation of an input frequency signal;

a voltage controlled oscillator receiving as an input an output of said phase detector; and

a 1-bit numerically controlled oscillator in a feedback loop between an output of said voltage controlled oscillator and a second input to said phase detector, said numerically controlled oscillator forming a frequency divider, said 1-bit numerically controlled oscillator including;

an adder receiving information stored in an input frequency register, and

a phase accumulator having an output fed back to said adder.

2. The digital phase locked loop according to claim 1, further comprising:

a loop filter between said phase detector and said voltage controlled oscillator.

5. The digital phase locked loop according to claim 1, further comprising:

a master reference clock configured to output an input master frequency signal; and

a reference divider configured to receive said input master frequency and to output said input frequency signal.

6. The digital phase locked loop according to claim 5, further comprising:

a charge pump between an output of said phase detector and an in put to a loop filter.

3. A digital phase locked loop, comprising:

a phase detector receiving at a first input a representation of an input frequency signal;

a voltage controlled oscillator receiving as an input an output of said phase detector; and

a numerically controlled oscillator in a feedback loop between an output of said voltage controlled oscillator and a second input to said phase detector, said numerically controlled oscillator forming a frequency divider; and

a pre-scaler in said feedback loop between said output of said voltage controlled oscillator and an input to said numerically controlled oscillator frequency divider.

4. The digital phase locked loop according to claim 3, further comprising:

a loop filter between said phase detector and said voltage controlled oscillator; and

a pre-scaler in said feedback loop between said output of said voltage controlled oscillator and an input to said numerically controlled oscillator frequency divider.

7. A method of providing feedback between an output signal of a voltage controlled oscillator and an input signal to a phase detector in a digital phase locked loop, comprising:

dividing said output signal from said voltage controlled oscillator with a 1-bit numerically controlled oscillator in a feedback loop, said 1-bit numerically controlled oscillator accumulating a phase output from a summer, and outputting said accumulated phase as a divided output signal; and

providing said divided output signal from said 1-bit numerically controlled oscillator in said feedback loop to said input of said phase detector.

8. The method of providing feedback between an output signal of a voltage controlled oscillator and an input signal to a phase detector in a digital phase locked loop according to claim 7, further comprising:

comparing a phase of said divided output signal to a phase of a representation of a master input frequency signal to determine a difference therebetween.

9. The method of providing feedback between an output signal of a voltage controlled oscillator and an input signal to a phase detector in a digital phase locked loop according to claim 8, further comprising:

changing a frequency of said output signal from said voltage controlled oscillator in accordance with said determined difference between said phase of said divided output signal and said phase of said representation of said master input frequency signal.

10. A method of providing feedback between an output signal of a voltage controlled oscillator and an input signal to a phase detector in a digital phase locked loop, comprising:

dividing said output signal from said voltage controlled oscillator with a numerically controlled oscillator in a feedback loop;

providing said divided output signal from said numerically controlled oscillator in said feedback loop to said input of said phase detector; and

pre-scaling said output signal from said voltage controlled oscillator before said step of dividing said output signal from said voltage controlled oscillator with said 1-bit numerically controlled oscillator.

11. Apparatus for providing feedback between an output signal of a voltage controlled oscillator and an input signal to a phase detector in a digital phase locked loop, comprising:

means for dividing said output signal from said voltage controlled oscillator with a 1-bit numerically controlled oscillator in a feedback loop, said 1-bit numerically controlled oscillator accumulating a phase output from a summer, and outputting said accumulated phase as a divided output signal; and

means for providing said divided output signal from said feedback loop to said input of said phase detector.

12. The apparatus for providing feedback between an output signal of a voltage controlled oscillator and an input signal to a phase detector in a digital phase locked loop according to claim 11, further comprising:

means for comparing a phase of said divided output signal to a phase of a representation of a master input frequency signal to determine a difference therebetween.

13. The apparatus for providing feedback between an output signal of a voltage controlled oscillator and an input signal to a phase detector in a digital phase locked loop according to claim 12, further comprising:

means for changing a frequency of said output signal from said voltage controlled oscillator in accordance with said determined difference between said phase of said divided output signal and said phase of said representation of said master input frequency signal.

14. Apparatus for providing feedback between an output signal of a voltage controlled oscillator and an input signal to a phase detector in a digital phase locked loop, comprising:

means for dividing said output signal from said voltage controlled oscillator with a numerically controlled oscillator in a feedback loop;

means for providing said divided output signal from said feedback loop to said input of said phase detector; and

pre-scaling said output signal from said voltage controlled oscillator before said step of dividing said output signal from said voltage controlled oscillator with said numerically controlled oscillator.