Hot-plug memory catridge power control logic

• US 6,651,138 B2
• Filed: 01/25/2001
• Issued: 11/18/2003
• Est. Priority Date: 01/27/2000
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Lai, Ho M., MacLaren, John M.
• Primary Examiner(s): Padmanabhan, Mano
• Assistant Examiner(s): Baker, Paul A
• Application Number:
  US09/770,101
• Publication Number:
  US 20020002690A1
• Time in Patent Office: 1,027 Days
• Field of Search: 711/115, 711/157, 711/114, 710/302, 714/799, 714/6
• US Class Current: 711/115
• CPC Class Codes: G06F 1/184 Mounting of motherboards
• CPC Class Codes: G06F 1/185 Mounting of expansion boards
• CPC Class Codes: G06F 1/186 Securing of expansion boards in correspondence to slots provided at the computer enclosure
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area

Abstract

A hot-pluggable memory cartridge for use in a redundant memory system. More specifically, the control logic and method for implementing a plurality of memory cartridges which may be hot-plugged into a memory sub-system.

Claims

1. A computer system comprising:

a host controller; and

a memory sub-system coupled to the host controller and configured to operate in a redundant mode of operation an a non-redundant mode of operation, the memory sub-system comprising;

a memory system board;

a plurality of memory cartridges coupled to the system board and configured to store data;

a plurality of cartridge connectors coupled to the memory system board, each of the plurality of cartridge connectors configured to receive one of the plurality of memory cartridges and further configure to facilitate the insertion and removal of the memory cartridges while the system is powered-up; and

a plurality of control logic devices coupled to the memory system board and configured to facilitate the transition of the memory sub-system from the redundant mode of operation to the non-redundant mode of operation, and further configured to facilitate the transition of the memory sub-system from the non-redundant mode of operation to the redundant mode of operation, the plurality of control logic devices comprising;

a first device programmed to facilitate the exchange of a first set of control signals between the host controller and the memory sub-system;

a plurality of power control devices coupled to the first device and configured to provide power fault detection in the computer system; and

a plurality of second devices coupled between the memory control device and the host controller and programmed to exchange a second set of control signals there between.

2. The computer system, as set forth in claim 1, wherein the host controller comprises error detection logic configured to detect errors in the data stored in the memory cartridges.

3. The computer system, as set forth in claim 1, wherein the host controller comprises a plurality of drivers configured to drive the plurality of control logic devices.

4. The computer system, as set forth in claim 1, wherein each of the plurality of memory cartridges comprises plurality of memory modules.

5. The computer system, as set forth in claim 4, wherein each of the plurality of memory cartridges comprises our memory modules.

6. The computer system, as set forth in claim 4, wherein each of the plurality of memory modules comprises a Dual Inline Memory Module (DIMM).

7. The computer system, as set forth in claim 4, wherein each of the plurality of memory modules comprises a plurality of memory devices configured to store data.

8. The computer system, as set forth in claim 7, wherein each of the plurality of memory devices comprises a Synchronous Dynamic Random Access Memory (SDRAM) device.

9. The computer system, as set forth in claim 1, wherein the memory sub-system comprises five memory cartridges.

10. The computer system, as set forth in claim 1, wherein each of the plurality of memory cartridges comprises a memory control device configured to control access to one of the plurality of memory cartridges.

11. The computer system, as set forth in claim 10, wherein each of the memory control devices comprises error detection logic configured to detect errors in the data stored in the plurality of memory cartridges.

12. The computer system, as set forth in claim 1, wherein each of the plurality of cartridge connectors comprises a plurality of pins of varying lengths.

13. The computer system, as set forth in claim 1, comprising a plurality of light emitting devices (LEDs) to indicate an insertion status of the memory cartridge.

14. The computer system, as set forth in claim 1, comprising a plurality of devices configured to provide an audio alarm for the memory sub-system, the alarm being activated in the event of an illegal memory cartridge removal.

15. The computer system, as set forth in claim 1, wherein the first device is a programmable array logic (PAL) device.

16. The computer system, as set forth in claim 1, wherein the first set of control signals comprise Present Detect signals, Power Fault signals, and Pre-Insertion Removal Notification Cable signals.

17. The computer system, as set forth in claim 1, wherein each of the plurality of power control devices is configured to facilitate a soft start of the memory cartridge.

18. The computer system, as set forth in claim 1, wherein each of the plurality of power control devices is configured to provide over-current protection for the memory cartridge.

19. The computer system, as set forth in claim 1, wherein each of the plurality of power control devices is configured to provide under-voltage protection for the memory cartridge.

20. The computer system, as set forth in claim 1, wherein each of the plurality of second devices comprises a programmable array logic (PAL) device.

21. The computer system, as set forth in claim 1, wherein the second set of control signals comprises a plurality of interrupt signals and a plurality of miscellaneous control signals.

22. A memory sub-system comprising:

a memory system board;

a plurality of memory cartridges coupled to the system board and configured to store data;

a plurality of cartridge connectors coupled to the memory system board, each of the plurality of cartridge connectors configured to receive one of the plurality of memory cartridges and further configured to facilitate the insertion and removal of the memory cartridges while the system is powered-up; and

a plurality of control logic devices coupled to the memory system board and configured to facilitate the transition of the memory sub-system from the redundant mode of operation to the non-redundant mode of operation, and further configured to facilitate the transition of the memory sub-system from the non-redundant mode of operation to the redundant mode of operation, the plurality of control logic devices comprising;

a first device programmed to facilitate the exchange of a first set of control signals between the host controller and the memory sub-system;

a plurality of power control devices coupled to the first device and configured to provide power fault detection in the computer system; and

a plurality of second devices coupled between the memory control device and the host controller and programmed to exchange a second set of control signals there between.

23. The computer system, as set forth in claim 22, wherein each of the plurality of memory cartridges comprises a plurality of memory modules.

24. The computer system, as set forth in claim 23, wherein each of the plurality of memory cartridges comprises four memory modules.

25. The computer system, as set forth in claim 23, wherein each of the plurality of memory modules comprises a Dual Inline Memory Module (DIMM).

26. The computer system, as set forth in claim 23, wherein each of the plurality of memory modules comprises a plurality of memory devices configured to store data.

27. The computer system, as set forth in claim 26, wherein each of the plurality of memory devices comprises a Synchronous Dynamic Random Access Memory (SDRAM) device.

28. The computer system, as set forth in claim 22, wherein the memory sub-system comprises five memory cartridges.

29. The computer system, as set forth in claim 22, wherein each of the plurality of memory cartridges comprises a memory control device configured to control access to one of the plurality of memory cartridges.

30. The computer system, as set forth in claim 29, wherein each of the memory control devices comprises error detection logic configured to detect errors in the data stored in the plurality of memory cartridges.

31. The computer system, as set forth in claim 22, wherein each of the plurality of cartridge connectors comprises a plurality of pins of varying lengths.

32. The computer system, as set forth in claim 22, comprising a plurality of light emitting devices (LEDs) to indicate an insertion status of the memory cartridge.

33. The computer system, as set forth in claim 22, comprising a plurality of devices configured to provide an audio alarm for the memory sub-system, the alarm being activated in the event of an illegal memory cartridge removal.

34. The computer system, as set forth in claim 22, wherein the first device is a programmable array logic (PAL) device.

35. The computer system, as set forth in claim 22, wherein the first set of control signals comprise Present Detect signals, Power Fault signals, and Pre-Insertion Removal Notification Cable signals.

36. The computer system, as set forth in claim 22, wherein each of the plurality of power control device is configured to facilitate a soft start of the memory cartridge.

37. The computer system, as set forth in claim 22, wherein each of the plurality of power control devices is configured to provide over-current protection for the memory cartridge.

38. The computer system, as set forth in claim 22, wherein each of the plurality of power control devices is configured to provide under-voltage protection for the memory cartridge.

39. The computer system, as set forth in claim 22, wherein each of the plurality of second devices comprises a programmable array logic (PAL) device.

40. The computer system, as set forth in claim 22, wherein the second set of control signals comprises a plurality of interrupt signals and a plurality of miscellaneous control signals.

41. A system configured to detect and protect a memory sub-system from failure mechanisms, the system comprising:

a first device programmed to facilitate the exchange of a first set of control signals between the host controller and the memory sub-system;

a plurality of power control devices coupled to the first device and configured to provide power fault detection in the computer system, and wherein each of the plurality of power control devices is configured to provide over-current protection for the memory cartridge; and

a plurality of second devices coupled between the memory control device and the host controller and programmed to exchange a second set of control signals there between.

42. The computer system, as set forth in claim 41, comprising a plurality of light emitting devices (LEDs) to indicate an insertion status of the memory cartridge.

43. The computer system, as set forth in claim 41, comprising a plurality of devices configured to provide an audio alarm for the memory sub-system, the alarm being activated in the event of an illegal memory cartridge removal.

44. The computer system, as set forth in claim 41, wherein the first device is a programmable array logic (PAL) device.

45. The computer system, as set forth in claim 41, wherein the first set of control signals comprise Present Detect signals, Power Fault signals, and Pre-Insertion Removal Notification Cable signals.

46. The computer system, as set forth in claim 41, wherein each of the plurality of power control devices is configured to facilitate a soft start of the memory cartridge.

47. The computer system, as set forth in claim 41, wherein each of the plurality of power control devices is configured to provide under-voltage protection for the memory cartridge.

48. The computer system, as set forth in claim 41, wherein each of the plurality of second devices comprises a programmable array logic (PAL) device.

49. The computer system, as set forth in claim 41, wherein the second set of control signals comprises a plurality of interrupt signals and a plurality of miscellaneous control signals.