High-speed memory controller for pipelining memory read transactions

• US 6,651,148 B2
• Filed: 05/22/2001
• Issued: 11/18/2003
• Est. Priority Date: 05/23/2000
• Status: Expired due to Term

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Widdup, Benjamin John
• Primary Examiner(s): Nguyen, Than
• Application Number:
  US09/861,576
• Publication Number:
  US 20020019911A1
• Time in Patent Office: 910 Days
• Field of Search: 710/240-244, 711/158, 711/167, 711/151
• US Class Current: 711/158
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36

Abstract

A memory controller (218) is disclosed which includes a write arbiter (130) and a read arbiter (140) for receiving and processing memory requests from a number of requestor modules (190) for accessing a high speed memory device (110). A high speed controller (120) controls data flow to and from the high speed memory device (110) at a frequency that is higher than ail operating of the arbiters (130, 140), allowing pseudo-simultaneous memory transactions. A read data dispatcher (160) is also disclosed for receiving data from the high speed controller (120) in response to read transactions and for passing the data to one of the requestor modules (190). The size and destination information for launched read transactions are kept by a queue 150. When return data is received by the read data dispatcher (160), the read data dispatcher (160) matches the appropriate amount of data with each queue entry and delivers that return data to the appropriate requester module (190).

Claims

1. A memory controller for controlling memory transactions to and from a memory device in response to memory requests from requestor modules, said memory controller comprising:

at least one arbiter for receiving and processing said memory requests, each memory request being received from a corresponding requestor module;

a controller module for issuing at least memory read transactions to said memory device in response to signals from said at least one arbiter;

an address memory means for receiving the addresses of said requestor modules initiating said memory read transactions in the order that said controller module issued said memory read transactions to said memory device, and for issuing said addresses in said order; and

a data dispatcher for receiving data from said controller module in response to said memory read transactions, for receiving a next address in said order from said address memory means, and for passing data associated with each memory read transaction to said corresponding requestor module, wherein said next address is used by said data dispatcher to identify said corresponding requestor module.

2. A memory controller as claimed in claim 1, wherein said at least one arbiter receives and processes at least one of said memory requests while said controller is still controlling data flow in response to a previous one of said signals.

3. A memory controller as claimed in claim 1, said controller module being configured to operate at a frequency that is higher than an operating frequency of said arbiter(s).

4. A memory controller as claimed in claim 3, wherein said controller module receives memory requests in adjacent high-speed controller clock cycles.

5. A method of launching memory transactions to and from a memory in response to memory requests from requestor modules without waiting for completion of a previous memory transaction, said method comprising the steps of:

receiving and processing said memory requests by at least one arbiter, each memory request being received from a corresponding requestor module;

issuing by a controller module at least memory read transactions to said memory device in response to signals from said at least one arbiter;

receiving and issuing by an address memory means the addresses of said requestor modules initiating said memory read transactions in the order that said controller module issued said memory read transactions to said memory device; and

receiving data from said controller module by a data dispatcher in response to said memory read transactions, receiving a next address in said order from said address memory means, and passing data associated with each memory read transaction to said corresponding requestor module, wherein said next address is used by said data dispatcher to identify said corresponding requestor module.

6. A method as claimed in claim 5, said controller module being configured to operate at a frequency that is higher than an operating frequency of said arbiter(s).

7. A method as claimed in claim 6, wherein said controller module receives memory requests in adjacent high-speed controller clock cycles.