Integrated circuit and smart card comprising such a circuit

• US 6,651,170 B1
• Filed: 01/04/1999
• Issued: 11/18/2003
• Est. Priority Date: 01/14/1998
• Status: Expired due to Fees

• Current Assignee: Irdeto B.V. (MultiChoice Group Ltd.)
• Original Assignee: Irdeto B.V. (MultiChoice Group Ltd.)
• Inventors: Rix, Simon Paul Ashley
• Primary Examiner(s): Barron, Gilberto
• Assistant Examiner(s): CALLAHAN, PAUL E
• Application Number:
  US09/224,904
• Time in Patent Office: 1,779 Days
• Field of Search: 380/264, 380/286, 380/44, 705/66, 705/41, 713/172, 713/193, 713/200
• US Class Current: 713/193
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G06Q 20/40975 using encryption therefor
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 9/0897 involving additional devices, e.g. trusted platform module [TPM], smartcard or USB

Abstract

An integrated circuit comprises a first processing unit and a non-volatile memory for storing a key. The first processing unit is arranged to carry out a cryptographic algorithm using the stored key. The non-volatile memory comprises at least two non-volatile memory elements, each memory element storing a share of a key used in the cryptographic algorithm. Each memory element is connected to the first processing unit by an independent bus.

Claims

1. An integrated circuit comprising a first processing unit and a non-volatile memory for storing a key, said first processing unit being arranged to carry out a cryptographic algorithm using said stored key, wherein said non-volatile memory comprises at least two non-volatile memory elements, each memory element storing a share of a key used in the cryptographic algorithm, wherein each memory element is connected to the first processing unit by an independent bus.

3. A smart card comprising an integrated circuit according to claim 1.

2. A method for carrying out a cryptographic algorithm using a key, wherein first and second shares of the key are stored in non-volatile memory elements, the first and second key shares are provided to a first processing unit through independent busses and the key shares are combined in said processing unit to carry out the cryptographic algorithm.