Automatic design of VLIW processors

• US 6,651,222 B2
• Filed: 02/06/2002
• Issued: 11/18/2003
• Est. Priority Date: 08/20/1999
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Schlansker, Michael S., Gupta, Shail Aditya, Kathail, Vinod K., Rau, B. Ramakrishna
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Whitmore, Stacy
• Application Number:
  US10/068,216
• Publication Number:
  US 20020120914A1
• Time in Patent Office: 650 Days
• Field of Search: 716/1, 716/2, 716/3, 716/13
• US Class Current: 716/102
• CPC Class Codes: G06F 2115/10 Processors
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A VLIW processor design system automates the design of programmable and non-programmable VLIW processors. The system takes as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints. With this input specification, the system constructs a datapath, including functional units, register files and their interconnect components from a macrocell database. The system uses the input and the datapath to generate an instruction format design. The instruction format may then be used to construct the processor control path. The abstract input and datapath may be used to extract a machine description suitable to re-target a compiler to the processor. To optimize the processor for a particular application program, the system selects custom instruction templates based on operation issue statistics for the application program generated by the re-targeted compiler.

Claims

1. An automated VLIW processor design method comprising:

programmatically extracting a machine description suitable to re-target a compiler from an input specification, including an opcode repertoire of a processor, an I/O format for operations in the opcode repertoire, instruction level parallelism constraints on the operations, and a register file specification;

from the compiler, re-targeted using the machine description of the processor, generating operation issue statistics for the specified operations; and

using the operation issue statistics, selecting custom instruction templates.

2. The method of claim 1 wherein an optimized instruction format specification for the processor is programmatically generated from an initial instruction format specification and an abstract instruction set specification;

wherein the initial instruction format specification includes instructions, bit fields for each of the instructions, and bit positions and bit encodings for each of the bit fields in the instruction; and

the abstract instruction set specification provides the opcode repertoire of the processor, the I/O format for operations in the opcode repertoire, the instruction level parallelism constraints on the operations, and the register file specification;

the method including;

using the abstract instruction set specification, the initial instruction format specification and the custom instruction templates, programmatically constructing a bit allocation problem specification identifying instruction fields that are to be assigned to bit positions in the instruction format of the processor, bit width requirements of the instruction fields, and instruction field conflict constraints; and

programmatically allocating bit positions in the processor to the instruction fields in the bit allocation problem specification to compute the optimized instruction format specification.

3. The method of claim 1 wherein an optimized instruction format specification for the processor is programmatically generated from an abstract instruction set specification;

wherein the abstract instruction set specification provides the opcode repertoire of the processor, the I/O format for operations in the opcode repertoire, the instruction level parallelism constraints on the operations, and the register file specification;

the method including;

using the abstract instruction set specification, and the custom instruction templates, programmatically constructing a bit allocation problem specification identifying instruction fields that are to be assigned to bit positions in the instruction format of the processor, bit width requirements of the instruction fields, and instruction field conflict constraints; and

programmatically allocating bit positions in the processor to the instruction fields in the bit allocation problem specification to compute the optimized instruction format specification.

4. The method of claim 1 wherein an optimized concrete instruction set architecture specification for the processor is programmatically generated from an initial concrete ISA specification, wherein the optimized concrete instruction set architecture specification includes a register file specification and an optimized instruction format specification;

programmatically extracting an abstract instruction set specification from the initial concrete ISA specification;

wherein the abstract instruction set specification provides the opcode repertoire of the processor, the I/O format for operations in the opcode repertoire, the instruction level parallelism constraints on the operations,

and the register file specification;

the method including;

using the abstract instruction set specification, and the custom instruction templates, programmatically constructing a bit allocation problem specification identifying instruction fields that are to be assigned to bit positions in the instruction format of the processor, bit width requirements of the instruction fields, and instruction field conflict constraints; and

programmatically allocating bit positions in the processor to the instruction fields in the bit allocation problem specification to compute the optimized instruction format specification.

5. A computer readable medium having software for performing the method of claim 1.

6. The method according to claim 1, wherein the operation issue statistics comprise a static histogram of combinations of operation groups.

7. The method according to claim 1, wherein the operation issue statistics comprise a dynamic histogram of combinations of operation groups.

8. The method according to claim 1 wherein selecting the custom instruction templates comprises selecting combinations of operation groups as potential candidates for the custom instruction templates and quantifying a cost function for each potential candidate.

9. The method according to claim 8 wherein said cost function quantifies code size.

10. The method according to claim 8 wherein said cost function quantifies decode complexity.

11. An automated VLIW processor design method for computing an optimized instruction format specification using an abstract instruction set specification, wherein the abstract instruction set specification provides the opcode repertoire of the processor, the I/O format for operations in the opcode repertoire, the instruction level parallelism constraints on the operations, and the register file specification, the method comprising:

programmatically selecting instruction templates for a processor design based on the abstract instruction set specification;

programmatically constructing a bit allocation problem specification identifying instruction fields that are to be assigned to bit positions in an instruction format of the processor design, bit width requirements of the instruction fields, and instruction field conflict constraints; and

programmatically allocating bit positions in the processor design to the instruction fields in the bit allocation problem specification to compute the optimized instruction format.

12. The method of claim 11 wherein the instruction templates define variable-length instructions.

13. The method of claim 11 wherein the instruction templates define fixed-length instructions.

14. The method of claim 11 wherein said constructing the bit allocation problem specification comprises constructing an instruction format tree data structure.

15. The method of claim 14 wherein one or more upper levels of the tree include the instruction templates and one or more lower levels of the tree include instruction fields.

16. The method of claim 15 wherein said constructing the bit allocation problem specification further comprises computing pairwise conflicts among the instruction fields.

17. The method of claim 16 wherein said constructing the bit allocation problem specification further comprises assigning instruction field affinities for instruction fields associated with common datapath resources.

18. The method of claim 17 wherein said allocating bit positions comprises allocating instruction fields with affinity to common instruction bits in one or more of the instruction templates.

19. The method of claim 11 wherein said allocating bit positions comprises allocating bits to left-most available positions in one or more of the instruction templates.

20. The method of claim 11 wherein said allocating bit positions comprises allocating bits to contiguous available positions in one or more of the instruction templates.