Radio frequency (RF) power devices having faraday shield layers therein

• US 6,653,691 B2
• Filed: 11/05/2001
• Issued: 11/25/2003
• Est. Priority Date: 11/16/2000
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Silicon Semiconductor Corporation
• Inventors: Baliga, Bantval Jayant
• Primary Examiner(s): Eckert, George
• Assistant Examiner(s): Ortiz, Edgardo
• Application Number:
  US09/993,412
• Publication Number:
  US 20020056883A1
• Time in Patent Office: 750 Days
• Field of Search: 257/328, 257/329, 257/335, 257/339, 257/401, 257/513, 257/390, 257/330, 438/270, 438/271, 438/589, 438/259
• US Class Current: 257/390
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/371 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/40095 Kinked
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/73255 Bump and strap connectors
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/84 using a strap connector
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/37 of an individual strap connector
• CPC Class Codes: H01L 24/40 of an individual strap connector
• CPC Class Codes: H01L 24/41 of a plurality of strap connectors
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0696 : of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/402 : Field plates
• CPC Class Codes: H01L 29/407 : Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 : for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/66712 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 : structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13063 : Metal-Semiconductor Field-Effect Transistor [MESFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/1903 : including wave guides
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

Integrated power devices include a plurality of field effect transistor unit cells and a Faraday shield layer that reduces parasitic gate-to-drain capacitance (Cgd) and concomitantly improves high frequency switching performance. These power devices may include a field effect transistor in an active portion of a semiconductor substrate and a gate electrode that is electrically connected to a gate of the field effect transistor. A Faraday shield layer is provided between at least a first portion of the gate electrode and a drain of the field effect transistor in order to capacitively decouple the first portion of the gate electrode from the drain. The gate electrode and drain typically extend adjacent opposing faces of the semiconductor substrate. The Faraday shield layer is preferably electrically connected to a source of the field effect transistor and provides edge termination.

Claims

1. An integrated power device, comprising:

a plurality of field effect transistor cells in an active portion of a semiconductor substrate;

a Faraday shield layer extending on a portion of the semiconductor substrate that is located outside a perimeter of the active portion;

a gate electrode that is electrically connected to each gate of said plurality of field effect transistor cells and extends outside the perimeter of the active portion in a manner that substantially confines it to within an outer perimeter of said Faraday shield layer;

an intermediate electrically insulating layer disposed between said Faraday shield layer and said gate electrode; and

a source electrode that is electrically coupled to each source of said plurality of field effect transistor cells and to said Faraday shield layer.

2. The device of claim 1, wherein said plurality of field effect transistor cells comprise vertical field effect transistor cells that extend between first and second opposing faces of the semiconductor substrate;

and wherein said Faraday shield layer extends opposite the first face and is separated therefrom by an underlying electrically insulating layer.

3. The device of claim 2, wherein said plurality of field effect transistor cells comprise a drain region extending adjacent the second face of the semiconductor substrate.

4. The device of claim 1, further comprising a gate electrode strip line that is electrically connected to said gate electrode and is at least substantially confined to within the outer perimeter of said Faraday shield layer.

5. The device of claim 3, further comprising an underlying electrically insulating layer extending between said Faraday shield layer and the semiconductor substrate;

and wherein said gate electrode is sufficiently confined within the outer perimeter of said Faraday shield layer that a capacitance between said gate electrode and the drain region is less than about 0.1 times a capacitance between a gate electrode and drain of an otherwise equivalent integrated power device that omits said Faraday shield layer and said intermediate electrically insulating layer from between said gate electrode and said underlying electrically insulating layer.

6. The device of claim 1, further comprising an underlying electrically insulating layer extending between said Faraday shield layer and the semiconductor substrate;

and wherein said gate electrode is sufficiently confined within the outer perimeter of said Faraday shield layer that a capacitance between said gate electrode and the drain region is less than about 0.1 times a capacitance between a gate electrode and drain of an otherwise equivalent integrated power device that omits said Faraday shield layer and said intermediate electrically insulating layer from between said gate electrode and said underlying electrically insulating layer.

7. The device of claim 1, further comprising:

a gate electrode strip line that is confined within the outer perimeter of said Faraday shield layer and has a first end electrically connected to said gate electrode; and

a gate pad that is electrically connected to a second end of said gate electrode strip line.

18. The device of claim 7, wherein the intermediate electrically insulating layer comprises a plurality of regions of different electrically insulating materials having different breakdown voltage characteristics.

8. An RF power device, comprising:

a field effect transistor in an active portion of a semiconductor substrate;

a Faraday shield layer extending on a portion of the semiconductor substrate that is located outside a perimeter of the active portion;

a gate electrode that is electrically connected to a gate of said field effect transistor and extends outside the perimeter of the active portion in a manner that substantially confines it to within an outer perimeter of said Faraday shield layer;

a gate electrode strip line that is electrically connected at a first end to said gate electrode and is substantially confined within the outer perimeter of said Faraday shield layer;

an intermediate electrically insulating layer disposed between said Faraday shield layer and said gate electrode; and

a source electrode that is electrically coupled to a source of said field effect transistor and to said Faraday shield layer.

9. The device of claim 8, wherein said intermediate electrically insulating layer extends between said Faraday shield layer and said gate electrode strip line.

10. The device of claim 9, further comprising a gate pad electrically connected to a second end of said gate electrode strip line;

and wherein said intermediate electrically insulating layer extends between said gate pad and said Faraday shield layer.

11. The device of claim 8, further comprising an underlying electrically insulating layer extending between said Faraday shield layer and the semiconductor substrate.

12. An RF power device, comprising:

a field effect transistor in an active portion of a semiconductor substrate;

a gate electrode that is electrically connected to a gate of said field effect transistor and extends outside a perimeter of the active portion of the semiconductor substrate;

a Faraday shield layer on the semiconductor substrate;

a gate electrode strip line that is electrically connected at a first end to said gate electrode and is substantially confined within an outer perimeter of said Faraday shield layer;

an intermediate electrically insulating layer disposed between said Faraday shield layer and said gate electrode strip line; and

a source electrode that is electrically coupled to a source of said field effect transistor and to said Faraday shield layer.

13. The device of claim 12, further comprising a gate pad electrically connected to a second end of said gate electrode strip line;

and wherein said intermediate electrically insulating layer extends between said gate pad and said Faraday shield layer.

14. The device of claim 12, further comprising an underlying electrically insulating layer extending between said Faraday shield layer and the semiconductor substrate.

15. A semiconductor switching device, comprising:

a vertical field effect transistor in an active portion of a semiconductor substrate;

a gate electrode that is electrically connected to a gate of said field effect transistor;

a Faraday shield layer that extends between at least a portion of said gate electrode and a drain of said field effect transistor and is electrically connected to a source of said vertical field effect transistor; and

a gate electrode strip line that extends on the semiconductor substrate and is electrically connected at a first end to said gate electrode.

16. The device of claim 15, wherein said Faraday shield layer extends between said gate electrode strip line and the drain of said vertical field effect transistor.

17. The device of claim 15, wherein said Faraday shield layer is separated from said gate electrode by an intermediate electrically insulating layer.

19. The device of claim 15, wherein said Faraday shield layer is separated from said gate electrode by an intermediate electrically insulating layer;

and wherein said gate electrode, the intermediate electrically insulating layer and said Faraday shield layer collectively form a metal oxide varistor.

20. The device of claim 19, wherein said intermediate electrically insulating layer comprises zinc oxide.

21. The device of claim 17, wherein said intermediate electrically insulating layer comprises intrinsic or P-type polycrystalline silicon;

wherein the gate of said field effect transistor is separated from the active portion of the semiconductor substrate by a gate oxide layer; and

wherein a thickness and/or material characteristic of said intermediate electrically insulating layer is such that its breakdown voltage is less than a breakdown voltage of the gate oxide layer.

22. The device of claim 17, wherein said intermediate electrically insulating layer comprises zinc oxide.

23. An integrated power device, comprising:

a plurality of field effect transistor cells in an active portion of a semiconductor substrate;

a Faraday shield layer extending on a portion of the semiconductor substrate that is located outside a perimeter of the active portion;

a gate electrode that is electrically connected to each gate of said plurality of field effect transistor cells and extends outside the perimeter of the active portion in a manner that substantially confines it to within an outer perimeter of said Faraday shield layer;

an intermediate electrically insulating layer disposed between said Faraday shield layer and said gate electrode;

a gate electrode strip line that extends on the semiconductor substrate and is electrically connected at a first end to said gate electrode;

a gate pad that is electrically connected to a second end of said gate electrode strip line; and

a source electrode that is electrically coupled to each source of said plurality of field effect transistors cells and to said Faraday shield layer.

24. The device of claim 23, wherein said Faraday shield layer extends between both said gate pad and gate electrode strip line and a drain of said plurality of field effect transistor cells.

25. The device of claim 24, wherein said intermediate electrically insulating layer provides electrostatic discharge protection to said plurality of field effect transistor cells.

26. The device of claim 25, wherein said intermediate electrically insulating layer comprises a plurality of regions of different electrically insulating materials having different breakdown voltage characteristics.

27. The device of claim 25, wherein said gate electrode, said intermediate electrically insulating layer and said Faraday shield layer collectively form a metal oxide varistor.

28. The device of claim 27, wherein said intermediate electrically insulating layer comprises zinc oxide.

29. The device of claim 25, wherein said intermediate electrically insulating layer comprises intrinsic or P-type polycrystalline silicon.

30. The device of claim 25, wherein said plurality of field effect transistor cells comprise vertical field effect transistor cells that extend between first and second opposing faces of the semiconductor substrate;

and wherein said Faraday shield layer extends opposite the first face and is separated therefrom by an underlying electrically insulating layer.

31. The device of claim 30, wherein no portion of said gate electrode extends outside the outer perimeter of said Faraday shield layer.

32. A RF power device, comprising:

a vertical power device in an active portion of a semiconductor substrate;

a gate electrode that is electrically connected to a gate of the vertical power device and extends outside a perimeter of the active portion;

a gate electrode strip line that extends on the semiconductor substrate and has a first end electrically connected to said gate electrode; and

a gate pad that extends on the semiconductor substrate and is electrically connected to a second end of said gate electrode strip line; and

a Faraday shield layer that extends between said gate electrode strip line and the semiconductor substrate.

33. The device of claim 32, wherein said Faraday shield layer extends between said gate electrode and the semiconductor substrate;

and wherein said gate electrode is patterned so that it is substantially confined within an outer perimeter of said Faraday shield layer.

34. The device of claim 32, wherein the vertical power device is an insulated-gate field effect transistor;

and wherein said Faraday shield layer is electrically connected to a source of the insulated-gate field effect transistor.

35. The device of claim 34, further comprising an intermediate electrically insulating layer extending between said Faraday shield layer and said gate electrode strip line;

and wherein said intermediate electrically insulating layer provides electrostatic discharge protection to the insulated-gate field effect transistor.

36. The device of claim 32, wherein said Faraday shield layer extends between said gate pad and the semiconductor substrate and is electrically connected to a terminal of said vertical power device.

37. The device of claim 36, further comprising an intermediate electrically insulating layer extending between said Faraday shield layer and said gate pad;

and wherein said intermediate electrically insulating layer provides electrostatic discharge protection to said vertical power device.

38. An RF power device, comprising:

a field effect transistor in an active portion of a semiconductor substrate;

a gate electrode strip line that is electrically connected at a first end to a gate of said field effect transistor;

a gate pad electrically connected to a second end of said gate electrode strip line; and

a Faraday shield layer extending between both said gate electrode strip line and said gate pad and a drain of said field effect transistor so that said gate electrode strip line and said gate pad are capacitively decoupled from the drain.

39. The device of claim 38, wherein said Faraday shield layer is electrically connected to a source of said field effect transistor.

40. An integrated circuit power device, comprising:

at least one field effect transistor cell in an active portion of a semiconductor substrate;

a Faraday shield layer extending on a portion of the semiconductor substrate that is located outside a perimeter of the active portion;

a gate electrode that is electrically connected to a gate in said at least one field effect transistor cell and extends outside the perimeter of the active portion in a manner that substantially confines it to within an outer perimeter of said Faraday shield layer;

an intermediate electrically insulating layer that is disposed between said Faraday shield layer and said gate electrode and is configured to provide ESD protection to the integrated power device by supporting a lower breakdown voltage between said gate electrode and said Faraday shield layer than is supported between the gate and the active portion; and

a source electrode that is electrically coupled to a source of said at least one field effect transistor cell and to said Faraday shield layer.

41. The device of claim 40, wherein said at least one field effect transistor cell comprises a vertical field effect transistor cell that extends between first and second opposing faces of the semiconductor substrate;

and wherein said Faraday shield layer extends opposite the first face and is separated therefrom by an underlying electrically insulating layer.

42. The device of claim 41, wherein said at least one field effect transistor cell comprises a drain region extending adjacent the second face of the semiconductor substrate.

43. The device of claim 40, further comprising:

a gate electrode strip line that is confined within the outer perimeter of said Faraday shield layer and has a first end electrically connected to said gate electrode; and

a gate pad that is electrically connected to a second end of said gate electrode strip line.

44. The device of claim 43, wherein said intermediate electrically insulating layer comprises a plurality of different insulating regions therein having different breakdown voltage characteristics.

45. The device of claim 44, wherein said gate electrode, said intermediate electrically insulating layer and said Faraday shield layer collectively form a metal oxide varistor.

46. The device of claim 40, wherein said intermediate electrically insulating layer comprises a plurality of different insulating regions therein having different breakdown voltage characteristics.

47. The device of claim 46, wherein said gate electrode, said intermediate electrically insulating layer and said Faraday shield layer collectively form a metal oxide varistor.

48. The device of claim 40, wherein said gate electrode, said intermediate electrically insulating layer and said Faraday shield layer collectively form a metal oxide varistor.

49. The device of claim 48, wherein said intermediate electrically insulating layer comprises zinc oxide.

50. The device of claim 40, wherein said intermediate electrically insulating layer comprises zinc oxide.

51. The device of claim 40, wherein said intermediate electrically insulating layer comprises intrinsic or P-type polycrystalline silicon;

wherein the gate is separated from the active portion by a gate insulating layer; and

wherein a thickness and/or material characteristic of said intermediate electrically insulating layer is such that its breakdown voltage is less than a breakdown voltage of the gate insulating layer.

52. A packaged power device, comprising:

an electrically conductive flange having a slot therein;

an electrically conductive substrate mounted within the slot;

a dielectric layer on said electrically conductive substrate;

a gate electrode strip line that is patterned on said dielectric layer and extends opposite the electrically conductive substrate;

a vertical power MOSFET having a source electrically coupled and mounted to a first portion of said flange located outside the slot and a gate electrode electrically coupled and mounted to a first end of said gate electrode strip line, said vertical power MOSFET comprising;

a Faraday shield layer that is electrically coupled to said source; and

an intermediate electrically insulating layer that is disposed between said Faraday shield layer and the gate electrode and is configured to provide ESD protection to the integrated power device by supporting a lower breakdown voltage between the gate electrode and said Faraday shield layer than is supported between a gate and active portion of said vertical power MOSFET.

53. The device of claim 52, further comprising:

a drain terminal mounted to said flange and electrically coupled to a drain of said vertical power MOSFET; and

a gate terminal mounted to said flange and electrically coupled to said gate electrode strip line.

54. The device of claim 53, further comprising a gate metal strap that electrically connects said gate terminal to a second end of said gate electrode strip line.

55. The device of claim 54, wherein the source of said vertical power MOSFET is electrically connected to the first portion of the flange by a first solder bond;

and wherein the gate electrode is electrically connected to the first end of said gate electrode strip line by a second solder bond.

56. The device of claim 52, wherein said electrically conductive substrate comprises a semiconductor substrate that is electrically connected to said flange.

57. The device of claim 56, further comprising a polysilicon capacitor electrode that is electrically connected to said gate electrode strip line.

58. The device of claim 57, wherein said polysilicon capacitor electrode, said dielectric layer and said semiconductor substrate collectively form a MOS capacitor.