Radio frequency (RF) power devices having faraday shield layers therein
First Claim
1. An integrated power device, comprising:
- a plurality of field effect transistor cells in an active portion of a semiconductor substrate;
a Faraday shield layer extending on a portion of the semiconductor substrate that is located outside a perimeter of the active portion;
a gate electrode that is electrically connected to each gate of said plurality of field effect transistor cells and extends outside the perimeter of the active portion in a manner that substantially confines it to within an outer perimeter of said Faraday shield layer;
an intermediate electrically insulating layer disposed between said Faraday shield layer and said gate electrode; and
a source electrode that is electrically coupled to each source of said plurality of field effect transistor cells and to said Faraday shield layer.
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Accused Products
Abstract
Integrated power devices include a plurality of field effect transistor unit cells and a Faraday shield layer that reduces parasitic gate-to-drain capacitance (Cgd) and concomitantly improves high frequency switching performance. These power devices may include a field effect transistor in an active portion of a semiconductor substrate and a gate electrode that is electrically connected to a gate of the field effect transistor. A Faraday shield layer is provided between at least a first portion of the gate electrode and a drain of the field effect transistor in order to capacitively decouple the first portion of the gate electrode from the drain. The gate electrode and drain typically extend adjacent opposing faces of the semiconductor substrate. The Faraday shield layer is preferably electrically connected to a source of the field effect transistor and provides edge termination.
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Citations
58 Claims
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1. An integrated power device, comprising:
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a plurality of field effect transistor cells in an active portion of a semiconductor substrate;
a Faraday shield layer extending on a portion of the semiconductor substrate that is located outside a perimeter of the active portion;
a gate electrode that is electrically connected to each gate of said plurality of field effect transistor cells and extends outside the perimeter of the active portion in a manner that substantially confines it to within an outer perimeter of said Faraday shield layer;
an intermediate electrically insulating layer disposed between said Faraday shield layer and said gate electrode; and
a source electrode that is electrically coupled to each source of said plurality of field effect transistor cells and to said Faraday shield layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 18)
a gate electrode strip line that is confined within the outer perimeter of said Faraday shield layer and has a first end electrically connected to said gate electrode; and
a gate pad that is electrically connected to a second end of said gate electrode strip line.
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18. The device of claim 7, wherein the intermediate electrically insulating layer comprises a plurality of regions of different electrically insulating materials having different breakdown voltage characteristics.
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8. An RF power device, comprising:
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a field effect transistor in an active portion of a semiconductor substrate;
a Faraday shield layer extending on a portion of the semiconductor substrate that is located outside a perimeter of the active portion;
a gate electrode that is electrically connected to a gate of said field effect transistor and extends outside the perimeter of the active portion in a manner that substantially confines it to within an outer perimeter of said Faraday shield layer;
a gate electrode strip line that is electrically connected at a first end to said gate electrode and is substantially confined within the outer perimeter of said Faraday shield layer;
an intermediate electrically insulating layer disposed between said Faraday shield layer and said gate electrode; and
a source electrode that is electrically coupled to a source of said field effect transistor and to said Faraday shield layer. - View Dependent Claims (9, 10, 11)
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12. An RF power device, comprising:
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a field effect transistor in an active portion of a semiconductor substrate;
a gate electrode that is electrically connected to a gate of said field effect transistor and extends outside a perimeter of the active portion of the semiconductor substrate;
a Faraday shield layer on the semiconductor substrate;
a gate electrode strip line that is electrically connected at a first end to said gate electrode and is substantially confined within an outer perimeter of said Faraday shield layer;
an intermediate electrically insulating layer disposed between said Faraday shield layer and said gate electrode strip line; and
a source electrode that is electrically coupled to a source of said field effect transistor and to said Faraday shield layer. - View Dependent Claims (13, 14)
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15. A semiconductor switching device, comprising:
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a vertical field effect transistor in an active portion of a semiconductor substrate;
a gate electrode that is electrically connected to a gate of said field effect transistor;
a Faraday shield layer that extends between at least a portion of said gate electrode and a drain of said field effect transistor and is electrically connected to a source of said vertical field effect transistor; and
a gate electrode strip line that extends on the semiconductor substrate and is electrically connected at a first end to said gate electrode. - View Dependent Claims (16, 17, 19, 20, 21, 22)
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23. An integrated power device, comprising:
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a plurality of field effect transistor cells in an active portion of a semiconductor substrate;
a Faraday shield layer extending on a portion of the semiconductor substrate that is located outside a perimeter of the active portion;
a gate electrode that is electrically connected to each gate of said plurality of field effect transistor cells and extends outside the perimeter of the active portion in a manner that substantially confines it to within an outer perimeter of said Faraday shield layer;
an intermediate electrically insulating layer disposed between said Faraday shield layer and said gate electrode;
a gate electrode strip line that extends on the semiconductor substrate and is electrically connected at a first end to said gate electrode;
a gate pad that is electrically connected to a second end of said gate electrode strip line; and
a source electrode that is electrically coupled to each source of said plurality of field effect transistors cells and to said Faraday shield layer. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31)
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32. A RF power device, comprising:
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a vertical power device in an active portion of a semiconductor substrate;
a gate electrode that is electrically connected to a gate of the vertical power device and extends outside a perimeter of the active portion;
a gate electrode strip line that extends on the semiconductor substrate and has a first end electrically connected to said gate electrode; and
a gate pad that extends on the semiconductor substrate and is electrically connected to a second end of said gate electrode strip line; and
a Faraday shield layer that extends between said gate electrode strip line and the semiconductor substrate. - View Dependent Claims (33, 34, 35, 36, 37)
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38. An RF power device, comprising:
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a field effect transistor in an active portion of a semiconductor substrate;
a gate electrode strip line that is electrically connected at a first end to a gate of said field effect transistor;
a gate pad electrically connected to a second end of said gate electrode strip line; and
a Faraday shield layer extending between both said gate electrode strip line and said gate pad and a drain of said field effect transistor so that said gate electrode strip line and said gate pad are capacitively decoupled from the drain. - View Dependent Claims (39)
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40. An integrated circuit power device, comprising:
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at least one field effect transistor cell in an active portion of a semiconductor substrate;
a Faraday shield layer extending on a portion of the semiconductor substrate that is located outside a perimeter of the active portion;
a gate electrode that is electrically connected to a gate in said at least one field effect transistor cell and extends outside the perimeter of the active portion in a manner that substantially confines it to within an outer perimeter of said Faraday shield layer;
an intermediate electrically insulating layer that is disposed between said Faraday shield layer and said gate electrode and is configured to provide ESD protection to the integrated power device by supporting a lower breakdown voltage between said gate electrode and said Faraday shield layer than is supported between the gate and the active portion; and
a source electrode that is electrically coupled to a source of said at least one field effect transistor cell and to said Faraday shield layer. - View Dependent Claims (41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51)
a gate electrode strip line that is confined within the outer perimeter of said Faraday shield layer and has a first end electrically connected to said gate electrode; and
a gate pad that is electrically connected to a second end of said gate electrode strip line.
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44. The device of claim 43, wherein said intermediate electrically insulating layer comprises a plurality of different insulating regions therein having different breakdown voltage characteristics.
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45. The device of claim 44, wherein said gate electrode, said intermediate electrically insulating layer and said Faraday shield layer collectively form a metal oxide varistor.
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46. The device of claim 40, wherein said intermediate electrically insulating layer comprises a plurality of different insulating regions therein having different breakdown voltage characteristics.
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47. The device of claim 46, wherein said gate electrode, said intermediate electrically insulating layer and said Faraday shield layer collectively form a metal oxide varistor.
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48. The device of claim 40, wherein said gate electrode, said intermediate electrically insulating layer and said Faraday shield layer collectively form a metal oxide varistor.
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49. The device of claim 48, wherein said intermediate electrically insulating layer comprises zinc oxide.
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50. The device of claim 40, wherein said intermediate electrically insulating layer comprises zinc oxide.
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51. The device of claim 40, wherein said intermediate electrically insulating layer comprises intrinsic or P-type polycrystalline silicon;
- wherein the gate is separated from the active portion by a gate insulating layer; and
wherein a thickness and/or material characteristic of said intermediate electrically insulating layer is such that its breakdown voltage is less than a breakdown voltage of the gate insulating layer.
- wherein the gate is separated from the active portion by a gate insulating layer; and
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52. A packaged power device, comprising:
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an electrically conductive flange having a slot therein;
an electrically conductive substrate mounted within the slot;
a dielectric layer on said electrically conductive substrate;
a gate electrode strip line that is patterned on said dielectric layer and extends opposite the electrically conductive substrate;
a vertical power MOSFET having a source electrically coupled and mounted to a first portion of said flange located outside the slot and a gate electrode electrically coupled and mounted to a first end of said gate electrode strip line, said vertical power MOSFET comprising;
a Faraday shield layer that is electrically coupled to said source; and
an intermediate electrically insulating layer that is disposed between said Faraday shield layer and the gate electrode and is configured to provide ESD protection to the integrated power device by supporting a lower breakdown voltage between the gate electrode and said Faraday shield layer than is supported between a gate and active portion of said vertical power MOSFET. - View Dependent Claims (53, 54, 55, 56, 57, 58)
a drain terminal mounted to said flange and electrically coupled to a drain of said vertical power MOSFET; and
a gate terminal mounted to said flange and electrically coupled to said gate electrode strip line.
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54. The device of claim 53, further comprising a gate metal strap that electrically connects said gate terminal to a second end of said gate electrode strip line.
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55. The device of claim 54, wherein the source of said vertical power MOSFET is electrically connected to the first portion of the flange by a first solder bond;
- and wherein the gate electrode is electrically connected to the first end of said gate electrode strip line by a second solder bond.
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56. The device of claim 52, wherein said electrically conductive substrate comprises a semiconductor substrate that is electrically connected to said flange.
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57. The device of claim 56, further comprising a polysilicon capacitor electrode that is electrically connected to said gate electrode strip line.
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58. The device of claim 57, wherein said polysilicon capacitor electrode, said dielectric layer and said semiconductor substrate collectively form a MOS capacitor.
Specification