Complementary metal oxide semiconductor with improved single event performance

• US 6,653,708 B2
• Filed: 07/30/2001
• Issued: 11/25/2003
• Est. Priority Date: 08/08/2000
• Status: Expired due to Fees

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Doyle, Brent R.
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Rao, Shrinivas H
• Application Number:
  US09/918,208
• Publication Number:
  US 20020020858A1
• Time in Patent Office: 848 Days
• Field of Search: 257/499, 257/544, 257/552, 257/593, 257/549, 257/370
• US Class Current: 257/499
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

Abstract

A junction isolated Complementary Metal Oxide Semiconductor (CMOS) transistor device includes a substrate of a first conductivity type and first and second buried layers formed within the substrate and having a second conductivity type opposite from the first conductivity type. First and second well regions of respective first and second conductivity are formed above respective first and second buried layers. An NMOS transistor and PMOS transistor are formed in the respective first and second well regions. The buried layer of the NMOS transistor is at −V (typically ground) and the buried layer of the PMOS transistor is biased at a positive supply voltage and spaced sufficiently from the NMOS transistor to improve single event effects occurrence.

Claims

1. A Complementary Metal Oxide Semiconductor (CMOS) transistor device comprising:

a substrate of a first conductivity;

an epitaxial silicon layer of second conductivity type formed over the substrate;

a single level buried layer formed from first and second electrically isolated buried layers lateral and adjacent to each other and formed within the epitaxial silicon layer and both having a second conductivity opposite from the first conductivity, wherein the first buried layer is connected to a circuit and ground and the second buried layer is connected to a positive supply voltage;

a first well region of first conductivity formed above the first buried layer and extending across a portion of the first buried layer;

a second well region of second conductivity formed above the second buried layer and extending across the second layer;

a third well region of second conductivity spaced laterally between the first and second well regions, wherein first and third well regions extend across the first buried layer;

a PMOS transistor formed above the second well region and connected to the positive supply voltage; and

an NMOS transistor formed above the first well region and spaced laterally from the PMOS transistor and separated by the third well region and forming a parasitic base and collector wherein the first well region biases the parasitic base and collector at the same potential such that current multiplication will not occur to decrease the gain of the parasitic bipolar transistor formed by the MOSFET source/drain regions, the MOSFET body as a well region, and the buried layer, and overcome a single event upset.

2. A device according to claim 1, wherein said first conductivity comprises a P-conductivity and said second conductivity comprises an N-conductivity.

3. A device according to claim 1, wherein said first conductivity comprises an N-conductivity and said second conductivity comprises a P-conductivity.

4. A device according to claim 1, and further comprising a body contact engaging said third well region off second conductivity.

5. A device according to claim 1, and further comprising a local oxidation of silicon that aids in separating the PMOS transistor from the NMOS transistor.

6. A device according to claim 1, and further comprising lightly doped drain structures formed within the respective NMOS and PMOS transistors.

7. A device according to claim 1, and further comprising a gate formed of a polysilicon layer, a spacer isolation, and gate oxide.

8. A device according to claim 1, and further comprising a suicide layer for shorting a source to body in the NMOS or PMOS transistors.

9. A Complementary Metal Oxide Semiconductor (CMOS) transistor device comprising:

a p-conductivity substrate;

an N-conductivity epitaxial silicon layer formed over the substrate;

a single level buried layer formed from first and second electrically isolated N-conductivity buried layers lateral and adjacent to each other and formed within the epitaxial silicon layer, wherein the first buried layer is connected to a circuit and ground and the second buried layer is connected to a positive supply voltage;

a first well region of P-conductivity formed above the first buried layer and extending across a portion of the first buried layer;

a second well region of N-conductivity formed above the second buried layer and extending across the second buried layer;

a third well region of N-conductivity spaced laterally between the first and second well regions wherein first and third well regions extend across the first buried layer;

a PMOS transistor formed above the second well region and connected to the positive supply voltage; and

an NMOS transistor formed above the first well region and spaced laterally from the PMOS transistor and separated by the third well region and forming a parasitic base and collector wherein the first well region biases the parasitic base and collector at the same potential such that current multiplication will not occur to decrease the gain of the parasitic bipolar transistor formed by the MOSFET source/drain regions, the MOSFET body as a well region, and the buried layer, and overcome a single event upset.

10. A device according to claim 9, and further comprising a body contact engaging said third well region.

11. A device according to claim 9, and further comprising a local oxidation of silicon that aids in separating the PMOS transistor from the NMOS transistor.

12. A device according to claim 9, and further comprising lightly doped drain structures formed within the respective NMOS and PMOS transistors.

13. A device according to claim 9, and further comprising a gate formed of a polysilicon layer, a spacer isolation, and gate oxide.

14. A device according to claim 9, and further comprising a suicide layer for shorting a source to body in the NMOS or PMOS transistors.