Three-dimensional memory array and method of fabrication

• US 6,653,712 B2
• Filed: 05/22/2002
• Issued: 11/25/2003
• Est. Priority Date: 04/28/2000
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Johnson, Mark, Knall, N. Johan
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Dolan, Jennifer M
• Application Number:
  US10/153,999
• Publication Number:
  US 20020140051A1
• Time in Patent Office: 552 Days
• Field of Search: 257/530, 257/202, 257/50, 257/74, 257/209, 257/529, 438/131, 438/129, 438/149, 438/622, 438/690, 438/467, 438/600, 365/130, 365/103, 365/51, 365/96, 365/105, 365/175
• US Class Current: 257/530
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 21/822 the substrate being a semiconductor, using silicon technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence

Abstract

A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally separated by an insulating layer used to form antifuses. In one embodiment, one-half the diode is located in one rail-stack and the other half in the other rail-stack.

Claims

1. A memory array disposed above a substrate comprising:

a first plurality of parallel spaced-apart rail-stacks disposed above the substrate running in a first direction;

a second plurality of parallel spaced-apart rail-stacks disposed above the first rail-stacks, the second plurality of rail-stacks running in a second direction different than the first direction such that a projection of the second rail-stack on the first rail-stack defines intersections with the first plurality of rail-stacks;

a layer of low conducting material separating the first plurality of rail-stacks from the second plurality of rail-stacks, the layer of low conducting material at each intersection of the first and second rail-stacks separating a first conductivity type doped silicon material in one of the first rail-stacks from a second conductivity type doped silicon material in one of the second rail-stacks; and

wherein the silicon on one side of each intersection is more lightly doped than the silicon on the opposite side of each intersection, such that the passage of a current equal to or greater than a predetermined threshold from one of the first rail-stacks to one of the second rail-stacks causes a diode to form at the intersection of these rail-stacks.

2. The memory array defined by claim 1 wherein the layer of low conducting material provides a physical barrier between the first and second plurality of rail-stacks, substantially minimizing sidewall leakage.

3. The memory array defined by claim 1 wherein the side of the intersection having the more lightly doped silicon includes a more heavily doped silicon region between the more lightly doped silicon and its respective conductor.

4. The memory array defined by claim 1 wherein the low conducting material comprises silicon dioxide.

5. The memory array defined by claim 1 wherein the low conducting material layer comprises silicon nitride.

6. The memory array defined by claim 1 wherein the low conducting material layer comprises undoped silicon.

7. The memory array defined by claim 1 wherein the first and second rail-stacks include a conductor comprising a metal or a metallic compound.

8. The memory array defined by claim 7 wherein each conductor is sandwiched between silicon in a multi-level array.

9. The memory array defined by claim 1 wherein the layer of low conductivity material is grown from a semiconductor layer.

10. In a multi-level memory having alternate levels of first spaced-apart conductors extending in one direction and second spaced-apart conductors in the other levels extending in a second direction, an improvement wherein each first conductor includes:

a first layer of a first conductivity type doped semiconductor material disposed on one side of the conductor over substantially its entire length;

a second layer of the first conductivity type doped semiconductor material disposed on the opposite side of the conductor over substantially its entire length;

a third layer of the first conductivity type doped semiconductor material disposed on the second layer over substantially its entire length, the third layer being more lightly doped than the second layer;

a first dielectric disposed in contact with the third layer;

a fourth layer of a second conductivity type doped semiconductor material disposed on one side of the second conductor over substantially its entire length;

a fifth layer of a second conductivity type doped semiconductor material disposed on the opposite side of the second conductor over substantially its entire length;

a sixth layer of the second conductivity type doped semiconductor material disposed on the fifth layer over substantially its entire length, the sixth layer being more lightly doped than the fifth layer; and

a second dielectric disposed in contact with the sixth layer.

11. The memory defined by claim 10 wherein the semiconductor material is silicon.

12. The memory defined by claim 11 wherein the dielectric is grown from the semiconductor material.

13. The memory defined by claim 12 wherein the dielectric is silicon dioxide.

14. The memory defined by claim 11 wherein the dielectric is silicon nitride.

15. The memory defined by claim 11 wherein the dielectric extends substantially continuously between the levels.

16. The memory defined by claims 10 or 11 wherein a third dielectric is disposed on the first layer.

17. The memory defined by claim 10 wherein the memory is programmed by forming Schottky diodes at selected intersections of the first and second conductors.

18. The memory defined by claim 10 wherein the second conductivity type doped material is doped silicon.

19. In a multi-level memory having alternate levels of first spaced-apart conductors extending in one direction and second spaced-apart conductors in the other levels extending in a second direction, an improvement wherein each first conductor includes:

a first layer of a first conductivity type doped semiconductor material disposed on one side of the first conductor over substantially its entire length;

a second layer of the first conductivity type doped semiconductor material disposed on the first layer over substantially its entire length, the second layer being more lightly doped than the first layer;

a first dielectric layer disposed in contact with the second layer; and

wherein only one of p+n−

diodes and p−

n+ diodes are formed at all levels of the array when programming occurs.

20. The memory defined by claim 19 wherein the semiconductor material is silicon.

21. The memory of claim 20 wherein the second conductors include:

a third layer of silicon doped with a second conductivity type dopant extending over substantially its entire length; and

a second dielectric layer disposed on the third layer.

22. The memory defined by claim 21 wherein additional silicon layers are disposed on the first and second dielectric layers.

23. The memory defined by claim 19 wherein the first dielectric layer at each level is silicon dioxide.

24. The memory defined by claim 23 wherein each dielectric layer is substantially continuous at each level.

25. The memory defined by claim 23 wherein the dielectric layer is grown from silicon.

26. The memory defined by claim 24 wherein the dielectric layer is blanket deposited.

27. The memory defined by claim 19 wherein the first dielectric layer at each level is silicon nitride.

28. A multi-level non-volatile memory array comprising:

a plurality of first rail-stacks disposed at a first and third level running generally in a first direction above a substrate, each rail-stack comprising first conductors sandwiched between layers of silicon doped with a first conductivity type dopant;

a plurality of second rail-stacks disposed at a second and fourth level above the substrate and running in a second direction, each of the second rail-stacks comprising second conductors sandwiched between layers of silicon doped with a second conductivity type dopant, and

a plurality of layers of dielectric each disposed respectively between successive levels of the first and second rail-stacks which are capable of being selectively breached to program the array.

29. The array defined by claim 28 wherein the layers of dielectric are blanket deposited.

30. The array defined by claim 28 wherein the layers of dielectric are grown on the silicon.

31. The array defined by claim 28 where the layers of dielectric are substantially continuous, forming a physical barrier between levels of rail-stacks.

32. The array defined by claim 28 wherein the layers of silicon on at least one side of the first conductors are more heavily doped adjacent to the first conductor than they are further from the first conductor.

33. The array defined by claim 32 wherein p+n−

diodes are formed at all levels of the array where programming occurs.

34. The array defined by claim 32 wherein p−

n+ diodes are formed at all levels of the array where programming occurs.

35. The array defined by claim 28 wherein the layers of silicon on at least one side of the second conductors are more heavily doped adjacent to the second conductors than they are further from the second conductors.

36. The array defined by claim 28 wherein the layer of dielectric comprises silicon dioxide.

37. The array defined by claim 28 wherein the layer of dielectric comprises silicon nitride.

38. The array defined by claim 28 wherein the first rail-stacks and second rail-stacks form right angles.

39. A multi-level non-volatile memory array comprising:

a plurality of first rail-stacks disposed at a first and third level running generally in a first direction above a substrate, each rail-stack comprising first conductors sandwiched between layers of silicon;

a plurality of second rail-stacks disposed at a second and fourth level above the substrate and running in a second direction, each of the second rail-stacks comprising second conductors sandwiched between layers of silicon,

a plurality of dielectric regions disposed between levels of the first and second rail-stacks which are capable of being selectively breached to program the array; and

where only one of p−

n+ diodes and p+n−

diodes are formed between each of the first and second rail-stacks where programming occurs.

40. The array defined by claim 39 wherein the dielectric regions are grown from one of the layers of silicon.

41. In a multi-level memory having alternate levels of first spaced-apart conductors extending in one direction and second spaced-apart conductors in the other levels extending in a second direction, an improvement wherein each of the first conductors includes:

a first layer of a first conductivity type doped semiconductor material disposed on one side of the first conductor over substantially its entire length;

a second layer of the first conductivity type doped semiconductor material disposed on the opposite side of the first conductor over substantially its entire length;

a third layer of the first conductivity type doped semiconductor material disposed on the first layer over substantially its entire length, the third layer being more lightly doped than the first layer;

a fourth layer of the first conductivity type doped semiconductor material disposed on the second layer over substantially its entire length, the fourth layer being more lightly doped than the second layer;

a first dielectric layer disposed in contact with the third layer;

a fifth layer of a second conductivity type doped material disposed on one side of the second conductor over substantially its entire length;

a sixth layer of the second conductivity type doped material disposed on the opposite side of the second conductor over substantially its entire length; and

a second dielectric layer disposed in contact with the sixth layer.

42. The memory of claim 41 wherein the dielectric layers are formed by blanket deposition.

43. The memory of claim 41 wherein the dielectric layers are grown.

44. The memory defined by claim 43 which the semiconductor material is silicon.

45. The memory defined by claim 44 wherein the dielectric is silicon nitride.

46. The memory of claim 41 wherein the first dielectric layer is substantially continuous over at least two spaced apart conductors extending in the one direction and at least two spaced apart conductors extending in the second direction.

47. The memory defined by claim 41 where the projection of the intersection of the first and second conductors at each level defines a p+n−

diode.

48. The memory defined in claim 41 wherein at the projection of the intersection of the first and second conductors at each level defines a p−

n+ diode.

49. The memory defined by claim 41 wherein the semiconductor material is silicon.

50. The memory defined by claim 49 wherein the dielectric is silicon dioxide.

51. A three dimensional memory array comprising:

a plurality of first spaced-apart parallel semiconductor rails doped with a first conductivity type dopant the first rails being disposed in a first direction and disposed at even levels in the array;

a plurality of second spaced-apart parallel semiconductor rails doped with a second conductivity type dopant, the second rails being disposed in a second direction different from the first direction and disposed as odd levels in the array; and

an anti-fuse layer separating at least the intersections of the first and second rails at each level.

52. The array defined by claim 51 wherein the first semiconductor rails are uniformly doped silicon rails.

53. The array defined by claim 52 wherein the second semiconductor rails are uniformly doped silicon rails.

54. The array defined by claim 51 wherein the antifuse layer is substantially continuous across the array.

55. The array defined by claims 52 or 53 wherein the antifuse material is a grown silicon dioxide layer.

56. The array defined by claims 51 or 53 wherein the antifuse material is a deposited silicon dioxide layer.

57. The array defined by claim 51 or 53 wherein the antifuse material is silicon nitride.

58. The array defined by claim 51 or 53 wherein the array is fabricated on a semiconductor substrate and each of the rails is coupled to circuitry in the substrate.

59. A multi-level non-volatile memory array comprising:

a plurality of first rail-stacks disposed at a first and third level running generally in a first direction above a substrate, each rail-stack comprising first conductors sandwiched between layers of silicon;

a plurality of second rail-stacks being thicker than the first rail-stack, disposed at a second and fourth level above the substrate and running in a second direction, each of the second rail-stacks comprising second conductors sandwiched between layers of silicon, and

a plurality of layers of dielectric each disposed respectively between successive levels of the first and second rail-stacks which are capable of being selectively breached to program the array.

60. The array defined by claim 59 wherein the layers of silicon on the first conductors are doped with a first conductivity type dopant and wherein the layers of silicon on the second conductor are doped with a second conductivity type dopant.

61. The array defined by claim 60 wherein the layers of silicon on at least one side of the first conductors are more heavily doped adjacent to the first conductor than they are further from the first conductor.

62. The array defined by claim 59 wherein p+n−

diodes are formed at all levels of the array where programming occurs.

63. The array defined by claim 59 wherein p−

n+ diodes are formed at all levels of the array where programming occurs.

64. The array defined by claims 59, 62, or 63 wherein the layer of dielectric comprises silicon dioxide.

65. The array defined by claim 59, 62, or 63 wherein the layer of dielectric comprises silicon nitride.

66. The array defined by claim 59, 62, or 63 wherein the first rail-stacks and second rail-stacks form right angles.