Semiconductor device and method for fabricating same

• US 6,653,731 B2
• Filed: 02/15/2001
• Issued: 11/25/2003
• Est. Priority Date: 02/28/2000
• Status: Expired due to Term

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: NEC Corporation
• Inventors: Kato, Yoshimasa, Tago, Masamoto
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Keshavan, Belur V
• Application Number:
  US09/784,490
• Publication Number:
  US 20010018229A1
• Time in Patent Office: 1,013 Days
• Field of Search: 257/737, 257/738, 257/778, 257/791-794, 438/108, 438/613
• US Class Current: 257/737
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68336 involving stretching of the auxiliary support post dicing
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A top surface of a LSI chip having a structure of a bare chip is provided with bumps, and a protective resin is provided for at least side surfaces of the LSI chips. The LSI chip is prevented from being chipped off or cracked because of protective resin provided for the side surfaces of the LSI chip. The invention provides a semiconductor device and a method for fabricating the same, in which the chip or a package thereof is prevented from being damaged, and thereby yield rate of the semiconductor device can be heightened. Since the numbers of the parts of the semiconductor device and the steps of using jigs and tools necessary for the fabrication process are reduced, fabricating cost of the semiconductor device can be cut down.

Claims

1. A semiconductor device, comprising

a bare chip;

plural bumps provided on an active surface of said bare chip; and

protective members formed on side surfaces and on said active surface of said bare chip between said plural bumps,

wherein said side surfaces of said protective members are substantially perpendicular to said active surface and a reverse surface opposite to said active surface of said bare chip, end surfaces of said protective members formed on said side surfaces of said bare chip and said reverse surface of said bare chip are on a common plane, and a sum of a thickness of each of said protective members formed on said side surfaces of said bare chip and a width of said bare chip is more than 100 μ

m.

2. The semiconductor device according to claim 1, wherein:

said protective member is further formed entirely on said reverse surface of said bare chip.

3. The semiconductor device according to claim 1, wherein:

said protective member is a resin.

4. The semiconductor device according to claim 1, wherein:

said bare chip is provided with intermediate electrodes inserted between electrodes connected with circuit patterns of said bare chip and said bumps.

5. A semiconductor device, comprising:

a bare chip;

plural bumps provided on an active surface of said bare chip; and

protective members formed on side surfaces of said bare chip to surround a periphery of said bare chip,

wherein a sum of a thickness of each of said protective members and a width of said bare chip is more than 100 μ

m.