Wafer integrated plasma probe assembly array

• US 6,653,852 B1
• Filed: 03/31/2000
• Issued: 11/25/2003
• Est. Priority Date: 03/31/2000
• Status: Expired due to Term

• Current Assignee: Lam Research Corporation
• Original Assignee: Lam Research Corporation
• Inventors: Benjamin, Neil
• Primary Examiner(s): Nguyen, Vinh P.
• Application Number:
  US09/540,418
• Time in Patent Office: 1,334 Days
• Field of Search: 324/754, 324/761, 324/158.1, 324/73.1, 438/14, 438/16, 438/18, 438/17, 439/482, 439/824
• US Class Current: 324/750.3
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A wafer integrated plasma diagnostic apparatus for semiconductor wafer processing system having a multiplicity of plasma probe assemblies arranged on a wafer in a planar array fashion such that one plasma probe assembly is in the center and eight more plasma probe assemblies are at intermediate positions such that they lie along the radius from the center to the corners; such corners forming four corners of a square box near the edge of the wafer. At each location and in each of the plasma probe assemblies, there are six possible probe elements having a relative geometrical area such that they are capable of making simultaneous measurements of both spatial resolution and real time measurement of different plasma characteristics at the wafer surface, such as: D.C. potential, A.C. potential, shading induced potentials, ion fluxes, ion energy distribution, and the electron part of the I-V Langmuir probe characteristic.

Claims

1. A wafer integrated plasma probe assembly array, comprising:

a larger probe;

four medium sized probes; and

and a smaller probe,

wherein said larger sized probe has a geometrical area equal to the geometric area of said four medium sized probes, and wherein said smaller probe has an area, which is one-hundredth the area of all said probes combined.

2. A wafer integrated plasma probe assembly array as in claim 1, wherein all the probes are Langmuir probes made from low impedance N-type Silicon.

3. A wafer integrated plasma probe assembly array as in claim 2, wherein said four medium sized probes are patterned probes.

4. A wafer integrated plasma probe assembly array as in claim 3, wherein all the Langmuir probes are smaller than an exposed substrate contact.

5. A wafer integrated plasma probe assembly array of claim 4, wherein the smaller probe has a geometrical area of about 0.25 square mm.

6. A wafer integrated plasma probe assembly array as in claim 5, wherein the exposed substrate contact is a low impedance ohmic contact.

7. A wafer integrated plasma probe assembly array as in claim 6, wherein patterning on said four medium sized probes constitutes four different aspect ratios.

8. A wafer integrated plasma probe assembly array, comprising:

a larger probe, four medium sized probes and a smaller probe;

said larger sized probe having a geometrical area equal to the geometric area of said four medium sized probes;

said medium sized probes being patterned probes; and

said smaller probe having a geometrical area of about 0.25 square mm.

9. A wafer integrated plasma probe assembly array as in claim 8, wherein all the probes are Langmuir probes made from low impedance N-type Silicon.

10. A wafer integrated plasma probe assembly array as in claim 9, wherein all the Langmuir probes are much smaller than an exposed substrate contact.

11. A wafer integrated plasma probe assembly array as in claim 10, wherein the exposed substrate contact is a low impedance ohmic contact.

12. A wafer integrated plasma probe assembly array as in claim 11, wherein said patterning on four medium sized probes constitutes four different aspect ratios.