Heterogeneous integrated circuit with reconfigurable logic cores

• US 6,653,859 B2
• Filed: 01/16/2002
• Issued: 11/25/2003
• Est. Priority Date: 06/11/2001
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Stollon, Neal S., Sihlbom, Bjorn, McCaughey, Thomas
• Primary Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US10/047,615
• Publication Number:
  US 20020186042A1
• Time in Patent Office: 678 Days
• Field of Search: 326/37-41, 326/44, 326/47, 326/101, 712/10, 712/15, 712/32, 712/35
• US Class Current: 326/38
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

A heterogeneous integrated circuit having a digital signal processor and two programmable logic cores, PLCs. An AMBA AHB couples the cores and most other functional units on the IC. The PLCs are also coupled to the DSP through a separate DMA sharing unit to the DSP, and particularly to the DSP memory. The memory sharing arrangement provides a separate high-speed data transfer mechanism between the PLCs and the DSP. The AMBA AHB allows the DSP to control the PLC operations without interference with high-speed data transfers. The DSP may reconfigure one PLC using the AMBA AHB, while it is processing data with the other PLC.

Claims

1. An integrated circuit comprising:

a common interface bus system,

a digital signal processor coupled to said common interface bus system,

a first programmable logic core having a configuration interface coupled to said common interface bus system and having a control interface coupled to said common interface bus system, and

a second programmable logic core having a configuration interface coupled to said common interface bus system and having a control interface coupled to said common interface bus system,

whereby said digital signal processor may control operation of one of said first and second programmable logic cores while the other of said first and second programmable logic cores is being reconfigured.

2. The integrated circuit of claim 1 further comprising:

a direct memory access device adapted for configuring programmable logic cores coupled to said common interface bus system,

whereby said digital signal processor may control operation of one of said first and second programmable logic cores while said direct memory access device configures the other of said first and second programmable logic cores.

3. The integrated circuit of claim 1 wherein:

said common interface bus system comprises a control bus and a configuration bus,

said digital signal processor is coupled to both said control bus and said configuration bus,

said first programmable logic core configuration interface is coupled to said configuration bus,

said first programmable logic core control interface is coupled to said control bus,

said second programmable logic core configuration interface is coupled to said configuration bus, and

said second programmable logic core control interface is coupled to said control bus.

4. The integrated circuit of claim 3, further comprising:

a direct memory access device adapted for configuring programmable logic cores coupled to both said control bus and said configuration bus,

whereby said digital signal processor may control operation of one of said first and second programmable logic cores while said direct memory access device configures the other of said first and second programmable logic cores.

5. The integrated circuit of claim 1 wherein said common interface bus system is an advanced microcontroller bus architecture advanced high-performance bus system.

6. The integrated circuit of claim 1 further comprising:

a memory coupled to said digital signal processor and to said first programmable logic core and said second programmable logic core,

whereby said digital signal processor may exchange data with said programmable logic cores independently of said common interface bus system.

7. The integrated circuit of claim 6 further comprising a multiplexor alternately coupling one of said first programmable logic core and said second programmable logic core to said memory.

8. The integrated circuit of claim 1 further comprising:

a third programmable logic core having a configuration interface coupled to said common interface bus system and having a control interface coupled to said common interface bus system, and

a fourth programmable logic core having a configuration interface coupled to said common interface bus system and having a control interface coupled to said common interface bus system,

whereby said digital signal processor may control operation of one of said third and fourth programmable logic cores while it configures the other of said third and fourth programmable logic cores.

9. A method for operating an integrated circuit having a digital signal processor, first and second programmable logic cores and a direct memory access device adapted for configuring said programmable logic cores comprising:

processing data with said digital signal processor and said first progammable logic core while using said direct memory access device to reconflaure said second programmable logic core.

10. A method for operating an integrated circuit having a digital signal processor comprising a processing core and memory and having first and second programmable logic cores comprising:

using a memory sharing unit to couple data between said first and second programmable logic cores and said memory;

using a common interface bus system to couple control and configuration signals between said digital signal processor and said first and second programmable logic cores; and

using said digital signal processor, said memory sharing unit and said first programmable logic core to process data while using said common interface bus system to reconfigure said second programmable logic core.

11. The method of claim 10, further comprising using said digital signal processor, said memory sharing unit and said second programmable logic core to process data while using said common interface bus system to reconfigure said first programmable logic core.

12. The method of claim 10, wherein said common interface bus system is an Advanced Microcontroller Bus Architecture Advanced High-performance Bus.

13. The method of claim wherein said common interface bus system comprises a control bus and a configuration bus and said programmable logic cores each have a control interface coupled to the control bus and a configuration interface coupled to the configuration bus, further comprising using a direct memory access device adapted for configuring programmable logic cores to reconfigure said second programmable logic core.

14. A method for operating an integrated circuit having a digital signal processor comprising a processing core and memory and having first, second, third and fourth programmable logic cores comprising:

using a memory sharing unit to couple data between said first, second, third and fourth programmable logic cores and said memory;

using a common interface bus system to couple control and configuration signals between said digital signal processor and said first, second, third and fourth programmable logic cores; and

using said digital signal processor, said memory sharing unit and said first and second programmable logic cores to process data while using said common interface bus system to reconfigure said third and fourth programmable logic cores.

15. The method of claim 14, further comprising using said digital signal processor, said memory sharing unit and said third and fourth programmable logic cores to process data while using said common interface bus system to reconfigure said first and second programmable logic cores.

16. The method of claim 14, wherein:

said first programmable logic core is used for preprocessing data and said second programmable logic core is used for postprocessing data; and

said third programmable logic core is reconfigured for preprocessing and said fourth programmable logic core is reconfigured for postprocessing.

18. The method of claim 14 wherein said common interface bus system comprises a control bus and a configuration bus and said programmable logic cores each have a control interface coupled to the control bus and a configuration interface coupled to the configuration bus, further comprising using a direct memory access device adapted for configuring programmable logic cores to reconfigure said third and fourth programmable logic cores.

17. The method of claim wherein said common interface bus system is Advanced Microcontroller Bus Architecture Advanced High-performance Bus.

19. An integrated circuit comprising:

an AMBA AHB bus,

a digital signal processor having an internal memory and a port coupled to said AMBA AHB bus,

a first programmable logic unit having a data port coupled to said digital signal processor internal memory, a configuration port coupled to said AMBA AHB bus and a control port coupled to said AMBA AHB bus, and

a second programmable logic unit having a data port coupled to said digital signal processor internal memory, a configuration port coupled to said AMBA AHB bus and a control port coupled to said AMBA AHB bus;

whereby said digital signal processor may process data with one of said first and second programmable logic units while reconfiguring the other of said first and second programmable logic units.

20. The integrated circuit 19, further comprising a memory sharing unit coupling the data ports of said first and second programmable logic units to said digital signal processor internal memory.