Multi-channel precision synchronous voltage-to-frequency converter

• US 6,653,872 B2
• Filed: 08/28/2001
• Issued: 11/25/2003
• Est. Priority Date: 09/01/2000
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: MacGugan, Douglas C.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Nguyen, Hai L.
• Application Number:
  US09/941,322
• Publication Number:
  US 20020027454A1
• Time in Patent Office: 819 Days
• Field of Search: 327/101, 327/100, 327/50, 327/56, 327/131, 327/105, 327/137, 327/135, 327/140, 327/113, 341/157
• US Class Current: 327/101
• CPC Class Codes: H03M 1/60 with intermediate conversion to frequency of pulses

Abstract

A multi-channel synchronous voltage-to-frequency converter (SVFC) realized in an integrated semiconductor circuit. The multi-channel SVFC having an operational amplifier adapted to receive an analog data signal to be converted and a reset signal, the operational amplifier integrating the sum of the analog signal and the reset signal and generating an output signal as a function of the integrated sum; a comparator coupled to receive the integrated sum and a reference level signal, the comparator outputting a logic level signal as a function of the received reference level signal; a digital logic circuit in response to an external clock signal, the digital logic circuit receiving the logic level signal and generating a reset control signal and a frequency output pulse as a function of the logic level signal; and a reset source switch receiving the reset control signal and outputting the reset signal.

Claims

1. A multi-channel SVFC (synchronous voltage-to-frequency converter) circuit, comprising:

a switchable input stage configured to exclusively receive a clocking signal input from a single external clock and to selectively receive one of a plurality of analog data signals on a plurality of different channels in response to the clocking signal;

an integrator adapted to receive the analog data signal from the switchable input stage and a reset signal, the integrator being structured to integrate the analog signal and generate an output signal as a function of the integrated analog signal;

a comparator coupled to receive the output signal from the integrator and a reference level signal, the comparator being set to trigger as a function of the received reference level signal and being structured to output a logic level signal as a function of the received integrator output signal;

a digital logic circuit responsive to the clocking signal, the digital logic circuit coupled to receive the logic level signal and structured to generate the reset control signal and a frequency output pulse on each of the channels as a function of the logic level signal and in phase with the clocking signal;

a timing circuit coupled to receive the input clocking signal from the single external clock, the timing circuit being structured to phase each of the frequency output pulses generated by the digital logic circuit as a function of a quantity of the plurality of different channels; and

a frequency output pulse buffer coupled to receive the frequency output pulse of each of the channels and being structured to generate ordered frequency output pulses in phase with the phased clocking signal.

2. The circuit of claim 1, wherein the integrator is an operational amplifier configured to receive the analog data signal from the switchable input stage and the reset signal.

3. The circuit of claim 1, wherein the switchable input stage further includes a trimming circuit coupled to an input of the integrator.

4. The circuit of claim 3, wherein the switchable input stage further includes selectively receiving a common reference level signal commonly received by each of the comparator, the non-inverting junction of the integrator, and the trimming circuit.

5. The circuit of claim 4 wherein the comparator is a fast response comparator set to trigger at the voltage reference level established by a voltage reference circuit.

6. The circuit of claim 1 wherein the switchable input stage includes a clock phasing circuit adapted to receive an external clock signal and output the clock signal controlling the digital logic circuit, the clock phasing circuit phasing a plurality of frequency output pulses generated by the digital logic circuit.

7. The circuit of claim 6 wherein the phasing the plurality of frequency output pulses generated by the digital logic circuit is a function of a desired number of output channels.

8. The circuit of claim 7 wherein the analog input signal includes a voltage reference signal.

9. The circuit of claim 1, further including a self-test circuit configured to generate a known input voltage to submit as an analog data signal to the integrator.

10. A method for-multi-channel synchronous voltage-to-frequency conversion comprising:

selecting an analog data signal from a plurality of analog data signals on a plurality of different channels based upon a receiving an external clocking signal;

integrating the analog data signal;

as a function of receiving a reference voltage, comparing the integrated analog data signal to the reference voltage;

changing state as a function of the reference voltage and outputting a state logic level signal;

as a function of the external clocking signal, generating a reset control signal and a plurality of frequency output pulses as a function of the state logic level signal;

phasing each of the frequency output pulses as a function of a quantity of the plurality of different channels; and

generating ordered frequency output pulses in phase with the phased external clocking signal; and

resetting the integrating as a function of the state logic level signal and in phase with the phased external clocking signal.

11. The method of claim 10 wherein the clock phasing is by means of digitally dividing and phase shifting in an electronic circuit.

12. The method of claim 10, further including self-testing by inputting a known voltage into the circuit.

13. A multiple input synchronous voltage-to-frequency converter, the converter comprising:

a switchable input output stage configured to receive a single external clock signal phased as a function of a plurality of input analog data signals and to select one of the plurality of analog data signals, and to select a corresponding one of a plurality of output buffers in response to the phased clock signal, each of the output buffers being structured to generate ordered frequency output pulses inphase with the phased clock signal,

an integrator, the integrator being configured to receive an analog signal at a first summing junction and a voltage reference signal, having a voltage value at a second summing junction, the integrator being further configured to output an output signal having a voltage value representative of integrated sums of the analog signal and the voltage reference signal, the integrator being still further configured to terminate a first integration and begin a second integration in response to receiving a reset signal at a reset terminal;

a comparator, the comparator configured to compare the voltage value of the output signal to the voltage value of the voltage reference signal and to change logical states at a comparator output terminal in response to the voltage value of the output signal exceeding the voltage value of the voltage reference signal; and

a logic section for generating a reset signal in response to the changed logical state at the comparator output terminal.

14. The converter of claim 13, wherein the logical section is further configured to store a frequency value in the buffer section.

15. The converter of claim 13, wherein the clock signal is phased by a clock phasing circuit, and wherein the number of phases corresponds to a number of the plurality of analog data signals.

16. The converter of claim 13, wherein the phased clock signal is generated by a digital divider and phase shifter circuit.

17. The converter of claim 13, wherein the phased clock signal is connected with the logical section such that the reset signals are in phase with the phase clock signal.