Large loading driver circuit with high speed and low crowbar current

• US 6,653,873 B1
• Filed: 07/19/2002
• Issued: 11/25/2003
• Est. Priority Date: 07/19/2002
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Nguyen, Andy T.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Nguyen, Hai L.
• Application Number:
  US10/198,942
• Time in Patent Office: 494 Days
• Field of Search: 327/227, 327/108-112, 327/172-176, 327/178, 327/261, 327/263, 327/264, 327/276-278, 327/284, 327/379, 327/383, 327/384, 327/391, 327/437, 326/21-24, 326/26, 326/27, 326/82, 326/83, 326/85, 326/89, 326/91
• US Class Current: 327/112
• CPC Class Codes: H03K 17/164 using parallel switching arrangements
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

A driver circuit drives heavily loaded signals at high speeds with a reduced crowbar current. One-shots are used to drive the output pullup and pulldown, thereby minimizing the period when both devices are turned on. One embodiment includes an inverter, a one-shot low, a one-shot high, a pullup, and a pulldown. An input signal drives the inverter and the two one-shots. The inverter output terminal is coupled to the driver output terminal, as are the pullup and pulldown. The one-shot low circuit controls the pullup. The one-shot high circuit controls the pulldown. Another embodiment includes two pre-driver circuits, one controlling an output pullup and the other controlling an output pulldown. Each of the pre-driver circuits is implemented using a one-shot low and a one-shot high, as described above. One such embodiment is an output driver for a PLD, and the one-shots include various programmable options.

Claims

1. A driver circuit, comprising:

a driver input terminal;

a driver output terminal;

a first inverter having an input terminal coupled to the driver input terminal and further having an output terminal coupled to the driver output terminal;

a first one-shot having an input terminal coupled to the driver input terminal and further having an output terminal;

a second one-shot having an input terminal coupled to the driver input terminal and further having an output terminal;

a first pullup coupled to the driver output terminal and having a control terminal coupled to the output terminal of the first one-shot; and

a first pulldown coupled to the driver output terminal and having a control terminal coupled to the output terminal of the second one-shot.

2. The driver circuit of claim 1, wherein the first and second one-shots are programmable.

3. The driver circuit of claim 2, wherein the first and second one-shots each comprise programmable means for disabling a one-shot function and enabling a delay function.

4. The driver circuit of claim 2, wherein the first and second one-shots each comprise programmable means for disabling a one-shot function and enabling a pass gate function.

5. The driver circuit of claim 2, wherein at least one of the first and second one-shots comprises programmable means for coupling the associated one-shot output terminal to a ground.

6. The driver circuit of claim 2, wherein at least one of the first and second one-shots comprises programmable means for coupling the associated one-shot output terminal to a power high.

7. The driver circuit of claim 1, wherein:

the first one-shot is a one-shot low;

the first pullup is a P-channel transistor coupled between a power high and the driver output terminal;

the second one-shot is a one-shot high; and

the first pulldown is an N-channel transistor coupled between the driver output terminal and a ground.

8. The driver circuit of claim 7, wherein the first one-shot comprises:

a non-inverting delay element having an input terminal coupled to the input terminal of the first one-shot and further having an output terminal;

a plurality of OR circuits coupled in series from a first OR circuit to a last OR circuit, the first OR circuit having a first input terminal coupled to the output terminal of the delay element, and a remainder of the OR circuits having a first input terminal coupled to an output terminal of a previous OR circuit, each OR circuit having a second input terminal coupled to the input terminal of the first one-shot; and

an output circuit having a first input terminal coupled to the input terminal of the first one-shot, a second input terminal coupled to an output terminal of the last OR circuit, and an output terminal coupled to the output terminal of the first one-shot.

9. The driver circuit of claim 8, wherein the output circuit comprises:

a first pass gate coupled between the input terminal and the output terminal of the first one-shot and having a control terminal coupled to the output terminal of the last OR circuit; and

a second pullup coupled to the output terminal of the first one-shot and having a control terminal coupled to the output terminal of the last OR circuit.

10. The driver circuit of claim 9, wherein the output circuit is programmable.

11. The driver circuit of claim 7, wherein the second one-shot comprises:

a non-inverting delay element having an input terminal coupled to the input terminal of the second one-shot and further having an output terminal;

a plurality of AND circuits coupled in series from a first AND circuit to a last AND circuit, the first AND circuit having a first input terminal coupled to the output terminal of the delay element, and a remainder of the AND circuits having a first input terminal coupled to an output terminal of a previous AND circuit, each AND circuit having a second input terminal coupled to the input terminal of the second one-shot; and

an output circuit having a first input terminal coupled to the input terminal of the second one-shot, a second input terminal coupled to an output terminal of the last AND circuit, and an output terminal coupled to the output terminal of the second one-shot.

12. The driver circuit of claim 11, wherein the output circuit comprises:

a first pass gate coupled between the input terminal and the output terminal of the second one-shot and having a control terminal coupled to the output terminal of the last AND circuit; and

a pulldown coupled to the output terminal of the second one-shot and having a control terminal coupled to the output terminal of the last AND circuit.

13. The driver circuit of claim 12, wherein the output circuit is programmable.

14. A driver circuit, comprising:

a driver input terminal;

a driver output terminal;

a first pre-driver circuit having an input terminal coupled to the driver input terminal and an output terminal;

a second pre-driver circuit having an input terminal coupled to the driver input terminal and an output terminal;

a first pullup coupled to the driver output terminal and having a control terminal coupled to the output terminal of the first pre-driver circuit; and

a first pulldown coupled to the driver output terminal and having a control terminal coupled to the output terminal of the second pre-driver circuit,

wherein the first and second pre-driver circuits each comprise;

a first inverter having an input terminal coupled to the input terminal of the pre-driver circuit and further having an output terminal coupled to the output terminal of the pre-driver circuit;

a first one-shot having an input terminal coupled to the input terminal of the pre-driver circuit and further having an output terminal;

a second one-shot having an input terminal coupled to the input terminal of the pre-driver circuit and further having an output terminal;

a second pullup coupled to the output terminal of the pre-driver circuit and having a control terminal coupled to the output terminal of the first one-shot; and

a second pulldown coupled to the output terminal of the pre-driver circuit and having a control terminal coupled to the output terminal of the second one-shot.

15. The driver circuit of claim 14, wherein the driver circuit is an output driver circuit for an integrated circuit (IC) device.

16. The driver circuit of claim 14, wherein in each of the first and second pre-driver circuits:

the first one-shot is a one-shot low;

the second pullup is a P-channel transistor coupled between a power high and the output terminal of the pre-driver circuit;

the second one-shot is a one-shot high; and

the second pulldown is an N-channel transistor coupled between the output terminal of the pre-driver circuit and a ground.

17. The driver circuit of claim 16, wherein in each of the first and second pre-driver circuits the first one-shot comprises:

a non-inverting delay element having an input terminal coupled to the input terminal of the first one-shot and further having an output terminal;

a plurality of OR circuits coupled in series from a first OR circuit to a last OR circuit, the first OR circuit having a first input terminal coupled to the output terminal of the delay element, and a remainder of the OR circuits having a first input terminal coupled to an output terminal of a previous OR circuit, each OR circuit having a second input terminal coupled to the input terminal of the first one-shot; and

an output circuit having a first input terminal coupled to the input terminal of the first one-shot, a second input terminal coupled to an output terminal of the last OR circuit, and an output terminal coupled to the output terminal of the first one-shot.

18. The driver circuit of claim 17, wherein the output circuit comprises:

a first pass gate coupled between the input terminal and the output terminal of the first one-shot and having a control terminal coupled to the output terminal of the last OR circuit; and

a third pullup coupled to the output terminal of the first one-shot and having a control terminal coupled to the output terminal of the last OR circuit.

19. The driver circuit of claim 18, wherein the output circuit is programmable.

20. The driver circuit of claim 16, wherein in each of the first and second pre-driver circuits the second one-shot comprises:

a non-inverting delay element having an input terminal coupled to the input terminal of the second one-shot and further having an output terminal;

a plurality of AND circuits coupled in series from a first AND circuit to a last AND circuit, the first AND circuit having a first input terminal coupled to the output terminal of the delay element, and a remainder of the AND circuits having a first input terminal coupled to an output terminal of a previous AND circuit, each AND circuit having a second input terminal coupled to the input terminal of the second one-shot; and

an output circuit having a first input terminal coupled to the input terminal of the second one-shot, a second input terminal coupled to an output terminal of the last AND circuit, and an output terminal coupled to the output terminal of the second one-shot.

21. The driver circuit of claim 20, wherein the output circuit comprises:

a first pass gate coupled between the input terminal and the output terminal of the second one-shot and having a control terminal coupled to the output terminal of the last AND circuit; and

a third pulldown coupled to the output terminal of the second one-shot and having a control terminal coupled to the output terminal of the last AND circuit.

22. The driver circuit of claim 21, wherein the output circuit is programmable.

23. An electronic system, comprising:

a first integrated circuit (IC) comprising an output pad and a driver circuit having an output terminal coupled to the output pad;

a second IC having an input pad; and

an interconnect coupling the output pad to the input pad,

wherein the driver circuit comprises;

a driver input terminal;

a first pre-driver circuit having an input terminal coupled to the driver input terminal and an output terminal;

a second pre-driver circuit having an input terminal coupled to the driver input terminal and an output terminal;

a first pullup coupled to the output terminal of the driver circuit and having a control terminal coupled to the output terminal of the first pre-driver circuit; and

a first pulldown coupled to the output terminal of the driver circuit and having a control terminal coupled to the output terminal of the second pre-driver circuit,

wherein the first and second pre-driver circuits each comprise;

a first inverter having an input terminal coupled to the input terminal of the pre-driver circuit and further having an output terminal coupled to the output terminal of the pre-driver circuit;

a first one-shot having an input terminal coupled to the input terminal of the pre-driver circuit and further having an output terminal;

a second one-shot having an input terminal coupled to the input terminal of the pre-driver circuit and further having an output terminal;

a second pullup coupled to the output terminal of the pre-driver circuit and having a control terminal coupled to the output terminal of the first one-shot; and

a second pulldown coupled to the output terminal of the pre-driver circuit and having a control terminal coupled to the output terminal of the second one-shot.

24. The electronic system of claim 23, wherein in each of the first and second pre-driver circuits:

the first one-shot is a one-shot low;

the second pullup is a P-channel transistor coupled between a power high and the output terminal of the pre-driver circuit;

the second one-shot is a one-shot high; and

the second pulldown is an N-channel transistor coupled between the output terminal of the pre-driver circuit and a ground.

25. The electronic system of claim 23, wherein the driver circuit is programmable.

26. The electronic system of claim 25, wherein the first IC is a programmable logic device (PLD), and the driver circuit is programmed by configuration data stored in configuration memory cells of the PLD.

27. The electronic system of claim 23, wherein the driver circuit is a tristateable driver circuit.