Voltage regulation

• US 6,653,891 B1
• Filed: 07/09/2002
• Issued: 11/25/2003
• Est. Priority Date: 07/09/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hazucha, Peter
• Primary Examiner(s): Zweizig, Jeffrey
• Application Number:
  US10/192,739
• Time in Patent Office: 504 Days
• Field of Search: 327/534, 327/535, 327/537, 327/540, 327/541
• US Class Current: 327/540
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence

Abstract

A voltage regulator for generating a constant output voltage. The voltage regulator includes an output stage having an internal feedback loop connected to control a current delivered to or received from a load to maintain the output voltage substantially constant relative to an internal reference voltage. The voltage regulator further includes a second feedback loop connected to control the internal reference voltage to cause the output voltage to track an external reference voltage.

Claims

1. A method comprising

controlling an output voltage to track a first reference voltage by

using a feedback loop to control a current delivered to or received from a load to tend to maintain the output voltage substantially constant relative to a second reference voltage, and

controlling the second reference voltage to cause the output voltage to track the first reference voltage.

2. The method of claim 1 in which controlling the second reference voltage comprises using a second feedback loop to control the second reference voltage based on a difference between the output voltage and the first reference voltage.

3. The method of claim 2 in which using the second feedback loop comprises using a differential amplifier to amplify a difference between the output voltage and the first reference voltage.

4. The method of claim 1 in which using the feedback loop comprises using a driving transistor, a level shifter, and a gain stage to control the current.

5. The method of claim 1, further comprising providing a supply voltage to a second load, the supply voltage having a voltage level different from the first reference voltage, and generating the output voltage from the supply voltage.

6. A method comprising

controlling an output voltage to track a first reference voltage by

using a feedback loop to control a current delivered to or received from a load to tend to maintain the output voltage substantially constant relative to a second reference voltage,

using a model of the feedback loop to generate an estimated output voltage that estimates the output voltage when the feedback loop delivers to or receives from the load a predetermined current, and

controlling the second reference voltage to cause the estimated output voltage to track the first reference voltage.

7. The method of claim 6 in which using the model comprises using a scaled replica of the feedback loop to generate the estimated output voltage.

8. The method of claim 6 in which controlling the second reference voltage comprises using an amplifier to generate the second reference voltage based on a difference between the estimated output voltage and the first reference voltage.

9. The method of claim 6, further comprising providing a supply voltage to a second load, the supply voltage having a voltage level different from the first reference voltage, and generating the output voltage from the supply voltage.

10. An apparatus comprising

a feedback loop connected to control a current delivered to or received from a load to maintain an output voltage substantially constant relative to a first reference voltage;

and

a circuit connected to control the first reference voltage to cause the output voltage to track a second reference voltage.

11. The apparatus of claim 10 in which the feedback loop comprises a driving transistor, a gain stage, and a level shifter.

12. The apparatus of claim 10 in which the feedback loop comprises a first transistor and a second transistor, the first and second transistors being P-type transistors and each having a drain, a source, and a gate, the drain of the first transistor being coupled to the source of the second transistor, the drain of the first transistor generating the output voltage, the gate of the second transistor being coupled to the first reference voltage, the drain of the second transistor being coupled to the gate of the first transistor.

13. The apparatus of claim 12 further comprising a third transistor coupled between the drain of the second transistor and the gate of the first transistor, the third transistor being an N-type transistor having a drain, a source, and a gate, the drain of the third transistor being coupled to the gate of the first transistor, the source of the third transistor being coupled to the drain of the second transistor, and the gate of the third transistor being coupled to a bias voltage.

14. The apparatus of claim 13 further comprising a first current source coupled to the drain of the second transistor and a second current source coupled to the drain of the third transistor.

15. The apparatus of claim 10 in which the circuit comprises an amplifier to amplify a difference between the output voltage and the first reference voltage.

16. The apparatus of claim 10 in which the feedback loop comprises a first transistor and a second transistor, the first and second transistors being N-type transistors each having a drain, a source, and a gate, the source of the first transistor being coupled to the drain of the second transistor, the drain of the second transistor generating the output voltage, the gate of the first transistor being coupled to the first reference voltage, the drain of the first transistor being coupled to the gate of the second transistor.

17. The apparatus of claim 16 further comprising a third transistor coupled between the drain of the first transistor and the gate of the second transistor, the third transistor being a P-type transistor having a drain, a source, and a gate, the drain of the third transistor being coupled to the gate of the second transistor, the source of the third transistor being coupled to the drain of the first transistor, and the gate of the third transistor being coupled to a bias voltage.

18. The apparatus of claim 17 further comprising a first current source coupled to the drain of the first transistor and a second current source coupled to the drain of the third transistor.

19. The apparatus of claim 10 further comprising a buffer stage coupled between the feedback loop and the circuit.

20. An apparatus comprising

a feedback loop connected to control a current delivered to or received from a load to maintain an output voltage substantially constant relative to a first reference voltage;

a first circuit connected to generate an estimated output voltage based on the first reference voltage, the estimated output voltage estimating the output voltage when the feedback loop delivers to or receives from the load a predetermined current; and

a second circuit connected to adjust the first reference voltage to control the first circuit to cause the estimated output voltage to track a second reference voltage.

21. The apparatus of claim 20 in which the feedback loop comprises a driving transistor, a gain stage, and a level shifter.

22. The apparatus of claim 20 in which the first circuit is a scaled replica of the feedback loop.

23. The apparatus of claim 20 in which the second circuit and the first circuit form a second feedback loop having a larger loop delay than the loop delay of the feedback loop connected to control the current.

24. The apparatus of claim 20 in which the second circuit comprises an amplifier that generates the first reference voltage based on a difference between the estimated output voltage and the second reference voltage.

25. The apparatus of claim 20 in which the feedback loop comprises a first transistor, a second transistor, and a third transistor, the first, second, and third transistors each having a drain, a source, and a gate, the drain of the first transistor being coupled to the source of the second transistor, the drain of the first transistor generating the output voltage, the gate of the first transistor being coupled to the drain of the third transistor, the drain of the second transistor being coupled to the source of the third transistor, the gate of the second transistor being coupled to the first reference voltage, the gate of the third transistor being coupled to a bias voltage.

26. The apparatus of claim 20 in which the feedback loop comprises a first transistor, a second transistor, and a third transistor, the first, second, and third transistors each having a drain, a source, and a gate, the source of the first transistor being coupled to the drain of the second transistor, the source of the first transistor generating the output voltage, the gate of the first transistor being coupled to the first reference voltage, the drain of the first transistor being coupled to the source of the third transistor, the gate of the second transistor being coupled to the drain of the third transistor, the gate of the third transistor being coupled to a bias voltage.

27. The apparatus of claim 20, further comprising a buffer stage coupled between the first circuit and the second circuit.

28. An apparatus comprising:

a circuit board;

an integrated circuit chip having

a first circuit designed to operate using a first supply voltage,

a second circuit designed to operate using a second supply voltage, and

a voltage regulator to generate the second supply voltage from the first supply voltage, the voltage regulator including

a feedback loop connected to control a current delivered to or received from the second circuit to maintain the second supply voltage substantially constant relative to a first reference voltage, and

a third circuit connected to control the first reference voltage to cause the second supply voltage to track a second reference voltage.

29. The apparatus of claim 28, further comprising a band-gap reference circuit to generate the second reference voltage.

30. The apparatus of claim 28, further comprising a power supply to generate the first supply voltage.

31. An apparatus, comprising:

a first circuit designed to operate using a first supply voltage;

a second circuit designed to operate using a second supply voltage; and

a voltage regulator to generate the second supply voltage from the first supply voltage, the voltage regulator including

a feedback loop connected to control a current delivered to or received from a load to maintain the second supply voltage substantially constant relative to a first reference voltage,

a third circuit connected to generate an estimated second supply voltage based on the first reference voltage, the estimated second supply voltage estimating the second supply voltage when the feedback loop delivers to or receives from the load a predetermined current; and

a fourth circuit connected to adjust the first reference voltage to control the third circuit to cause the estimated second supply voltage to track a second reference voltage.

32. The apparatus of claim 31 in which the first circuit comprises a data processor.

33. The apparatus of claim 31 in which the second circuit comprises a memory.