Integrated current mirror in output stage of operational amplifier

• US 6,653,894 B2
• Filed: 04/18/2002
• Issued: 11/25/2003
• Est. Priority Date: 04/19/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Botker, Thomas L.
• Primary Examiner(s): Choe, Henry
• Application Number:
  US10/125,971
• Publication Number:
  US 20030197555A1
• Time in Patent Office: 586 Days
• Field of Search: 330/9, 330/253, 330/255, 330/257, 330/258, 330/261, 330/288, 330/290
• US Class Current: 330/9
• CPC Class Codes: H03F 1/02 Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• CPC Class Codes: H03F 2200/261 Amplifier which being suitable for instrumentation applications
• CPC Class Codes: H03F 2203/45674 the LC comprising one current mirror
• CPC Class Codes: H03F 2203/45726 the LC comprising more than one switch, which are not cross coupled
• CPC Class Codes: H03F 3/303 using opamps as driving stages
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit

Abstract

A current mirror configuration can be integrated in the output stage of an operational amplifier that enables rail-to-rail performance without requiring a significant increase in headroom. The operational amplifier can be configured with a chopper stabilized current mirror configured within the output stage of the operational amplifier. Through use of the integrated current mirror in the output stage of the amplifier, the substrate of the integrated circuit can be suitably grounded to minimize noise problems. To obtain rail-to-rail output performance, the operational amplifier can incorporate a positive and negative charge pump. However, rather than requiring the negative charge pump to charge pump the operational amplifier negative for a full V_GS voltage, such as in a conventional current mirror, the integrated current mirror requires minimal headroom for implementation with the operational amplifier. For example, the current mirror enables the charge pump to only charge pump the operational amplifier negative by approximately ½ V_BE voltage so that the NMOS source-drain diffusions are not forward-biased to the grounded substrate.

Claims

1. An operational amplifier circuit configured for increasing rail-to-rail output performance, said operational amplifier circuit comprising:

an amplifier having a gain stage configured for receiving an input signal and having an output stage configured for providing an amplifier output signal;

a first current mirror circuit comprising a first transistor and a second transistor, said first current mirror circuit having an output device integrated within said output stage of said amplifier;

a second current mirror circuit comprising a third transistor and a fourth transistor, said second current mirror circuit having an output device integrated within said output stage of said amplifier; and

wherein said first current mirror circuit and said second current mirror circuit are configured to mirror said input signal to provide said amplifier output signal for driving a load;

said amplifier further comprising an output biasing network within said output stage and configured between said gain stage and said output devices of said first current mirror circuit and said second current mirror circuit; and

a first switch network coupled to said first current mirror circuit, and a second switch network coupled to said second current mirror circuit, wherein said first switch network and said second switch network are configured to provide chopper stabilization within a feedback loop to said first current mirror circuit and said second current mirror circuit.

2. An operational amplifier circuit according to claim 1, wherein said operational amplifier circuit further comprises:

first switch network being configured to permit said first transistor to drive a first voltage output terminal and to permit said second transistor to drive a second voltage output terminal during a first phase of operation, and to permit said second transistor to drive said first voltage output terminal and to permit said first transistor to drive said second voltage output terminal during a second phase of operation; and

said second switch network being configured to permit said third transistor to drive said first voltage output terminal and to permit said fourth transistor to drive said second voltage output terminal during said first phase of operation, and to permit said fourth transistor to drive said first voltage output terminal and to permit said third transistor to drive said second voltage output terminal during said second phase of operation; and

wherein said first switch network and said second switch network facilitate reduction of mismatch errors between transistors of at least one of said first current mirror circuit and said second current mirror circuit.

3. An operational amplifier circuit according to claim 2, wherein said first output voltage terminal is coupled back to an inverting input terminal of said gain stage.

4. An operational amplifier circuit according to claim 2, wherein said first transistor and said second transistor have gates coupled to said output biasing network, sources coupled together, and drains alternately coupled through said first switch network to one of said first output voltage terminal and said second output voltage terminal.

5. An operational amplifier circuit according to claim 4, wherein said third transistor and said fourth transistor have gates coupled to said output biasing network, sources connected together, and drains alternately coupled through said second switch network to one of said first output voltage terminal and said second output voltage terminal.

6. An operational amplifier circuit according to claim 2, wherein said output biasing network comprises a class AB biasing network coupled to gates of said first transistor, said second transistor, said third transistor and said fourth transistor and to said gain stage, said AB biasing network being configured to provide biasing to said output stage.

7. An operational amplifier circuit according to claim 2, wherein said amplifier circuit further comprises:

a first pair of cascode devices coupled between said first output voltage terminal and said second output voltage terminal and said first switch network, said first pair of cascode devices being configured to minimize output impedance differences and improve matching between said first transistor and said second transistor; and

a second pair of cascode devices coupled between said first output voltage terminal and said second output voltage terminal and said second switch network, said second pair of cascode devices being configured to minimize output impedance differences and improve matching between said third transistor and said fourth transistor.

8. A chopper stabilized current mirror configuration comprising:

a first integrated current mirror circuit comprising a first transistor and a second transistor, said first transistor and said second transistor having gates connected together and having sources coupled together;

a first switch network coupled to drains of said first transistor and said second transistor, said first switch network configured for chopper stabilizing said first transistor and said second transistor;

a second integrated current mirror circuit comprising a third transistor and a fourth transistor, said third transistor and said fourth transistor having gates connected together and having sources coupled together;

a second switch network coupled to drains of said third transistor and said fourth transistor, said second switch network configured for chopper stabilizing said third transistor and said fourth transistor; and

wherein said first switch network and said second switch network are configured to permit said first transistor and said third transistor to drive current to a first output terminal and said second transistor and said fourth transistor to drive current to a load device during a first phase of operation, and are configured to permit said second transistor and said fourth transistor to drive current to said first output terminal and said first transistor and said third transistor to drive current to the load device during a second phase of operation.

9. The chopper stabilized current mirror configuration according to claim 8, wherein said chopper stabilized current mirror configuration further comprises:

a first pair of cascode devices coupled between said first output terminal and the load device and said first switch network, said first pair of cascode devices being configured to force voltages across said first transistor and said second transistor to be approximately equal; and

a second pair of cascode devices coupled between said first output terminal and the load device and said second switch network, said second pair of cascode devices being configured to force voltages across said third transistor and said fourth transistor to be approximately equal.

10. The chopper stabilized current mirror configuration according to claim 8, wherein said first current mirror circuit comprise NMOS devices, and said second current mirror circuit comprise PMOS devices.

11. The chopper stabilized current mirror configuration according to claim 8, wherein said first current mirror circuit and said first switch network can be configured in a feedback arrangement with an amplifier to permit the amplifier circuit to obtain full rail-to-rail output performance by charge pumping said first integrated current mirror circuit and said second integrated current mirror circuit by at least approximately ½

V_BE.

12. An integrated circuit comprising:

an amplifier having a gain stage and an output stage;

a current mirror having a first transistor and a second transistor, said current mirror integrated within said output stage of said amplifier such that at least one of said first transistor and said second transistor comprises an output transistor and another of said first transistor and said second transistor comprises a mirroring device for said amplifier, wherein current from said output transistor is mirrored through said mirroring device to a load;

a second current mirror having a third transistor and a fourth transistor, said second current mirror integrated within said output stage of said amplifier such that at least one of said third transistor and said fourth transistor comprise a second output transistor and another of said third transistor and said fourth transistor comprises a second mirroring device for said amplifier, wherein current from said second output transistor is mirrored through said second mirroring device to said load; and

a first switch network coupled to drains of said first transistor and said second transistor, said first switch network configured for chopper stabilizing said first transistor and said second transistor, said first switch network configured to permit said first transistor to drive current to a first output terminal and to permit said second transistor to drive current to a load device during a first phase of operation, and configured to permit said second transistor to drive current to said first output terminal and said first transistor to drive current to the load device during a second phase of operation.

13. An integrated circuit according to claim 12, said amplifier further comprising an output biasing network configured between said gain stage and said output stage.

14. An amplifier circuit configured for providing full rail-to-rail output performance, said amplifier circuit comprising:

an amplifier having a gain stage configured for receiving an input signal;

at least one current mirror configuration integrated within said amplifier, said at least one current mirror comprising a first transistor device and a second transistor device; and

at least one switching network, said at least one switching network configured such that said first transistor device is coupled in a feedback arrangement with said amplifier and said second transistor device is configured to mirror said input signal to an output load during a first phase, and said second transistor device is coupled in a feedback arrangement with said amplifier and said first transistor device is configured to mirror said input signal to the output load during a second phase.

15. The amplifier circuit according to claim 14, wherein said at least one current mirror configuration comprises a first current mirror configuration comprising said first transistor device and said second transistor device, and said at least one switching network comprises a first switching network, and wherein said amplifier circuit further comprises:

a second current mirror configuration integrated within said amplifier, said second current mirror comprising a third transistor device and a fourth transistor device; and

a second switching network configured such than said third transistor device is coupled in a feedback arrangement with said amplifier and said fourth transistor device is configured to mirror said input signal to an output load during said first phase, and said fourth transistor device is coupled in a feedback arrangement with said amplifier and said third transistor device is configured to mirror said input signal to the output load during said second phase.

16. An amplifier circuit according to claim 14, wherein said first transistor and said second transistor have gates coupled to an output biasing network, sources connected together, and drains alternately coupled through said first switch network to one of said feedback arrangement and the output load.

17. An amplifier circuit according to claim 16, wherein said third transistor and said fourth transistor have gates coupled to an output biasing network, sources connected together, and drains alternately coupled through said second switch network to one of said feedback arrangement and the output load.

18. An amplifier circuit according to claim 17, wherein said output biasing network further comprises an AB biasing network being configured to provide biasing to said output stage.

19. An amplifier circuit according to claim 15, wherein said amplifier circuit further comprises:

a first pair of cascode devices having a first cascode device coupled to said first switch network in said feedback arrangement, and a second cascode device coupled between the load device and said first switch network, said first pair of cascode devices being configured to minimize output impedance differences and improve matching between said first transistor and said second transistor; and

a second pair of cascode devices having a third cascode device coupled to said second switch network in said feedback arrangement, and a fourth cascode device coupled between the load device and said second switch network, said second pair of cascode devices being configured to minimize output impedance differences and improve matching between said third transistor and said fourth transistor.

20. A method for chopper stabilizing a current mirror configuration to facilitate full rail-to-rail output performance in an amplifier circuit, said method comprising the steps of:

receiving an input current signal in an amplifier having an output stage configured within a first current mirror circuit and a second current mirror circuit;

switching a first transistor of said first current mirror circuit and a third transistor of said second current mirror circuit to be in a feedback arrangement with said amplifier during a first phase of operation;

switching a second transistor of said first current mirror circuit and a fourth transistor of said second current mirror circuit to be connected with a load device during said first phase of operation;

switching said second transistor of said first current mirror circuit and said fourth transistor of said second current mirror circuit to be in said feedback arrangement with said amplifier device during a second phase of operation; and

switching a first transistor of said first current mirror circuit and a third transistor of said second current mirror circuit to be connected with the load device during said first phase of operation.