High efficiency stage-switching CDMA power amplifier

• US 6,653,898 B2
• Filed: 12/28/2000
• Issued: 11/25/2003
• Est. Priority Date: 12/28/2000
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Monroe, Robert W.
• Primary Examiner(s): Shingleton, Michael B
• Application Number:
  US09/752,903
• Publication Number:
  US 20020084844A1
• Time in Patent Office: 1,062 Days
• Field of Search: 330/51, 330/124.R, 330/129, 330/136, 330/284
• US Class Current: 330/51
• CPC Class Codes: H03F 1/0266 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04

Abstract

There is disclosed for use in a base station power amplifier a first and second amplifier stage for amplifying a received RF signal. A controller is provided that samples the incoming signal to determine its power level. If the signal power level is below a predetermined threshold, the controller directs the signal to the first amplifier stage which provides low power amplification. If the signal is above the threshold, the controller passes the signal to the second amplifier stage for high power amplification. Power efficiency is increased and DC power is reduced by switching off the unused amplifier stage.

Claims

1. For use in a base station of a wireless communications network, a system for enhancing power amplifier efficiency comprising:

a first amplifier stage and a second amplifier stage for amplifying received signal; and

a controller for directing said signal to one of said first and second amplifier stages according to a predetermined threshold, wherein said controller comprises a first set of pin-diode switches in conjunction with quarter-wavelength lines for opening and closing a radio frequency input for said first amplifier stage.

2. The system as set forth in claim 1, further comprising a second set of pin-diode switches in conjunction with quarter-wavelength lines for opening and closing said radio frequency input for said second amplifier stage.

3. The system as set forth in claim 1, further comprising a time delay circuit for delaying a radio frequency signal.

4. The system as set forth in claim 1, further comprising:

a detection circuit for sampling said radio frequency signal to determine a power level of said signal; and

a switch for switching said signal to one of said first amplifier stage and said second amplifier stage.

5. The system as set forth in claim 4, further comprising a circuit for switching said incoming signal to said first amplifier stage for processing radio frequency signals below a predetermined power level.

6. The system as set forth in claim 4, further comprising a circuit for switching said incoming signal to said second amplifier stage for processing said radio frequency signals above a predetermined power level.

7. A wireless communications network comprising:

a plurality of base stations capable of communicating with a plurality of mobile stations disposed in a coverage area of said wireless communications network, wherein at least one of said base stations comprises a system for enhancing power amplifier efficiency, said system comprising;

a first amplifier stage and a second amplifier stage for amplifying a received signal; and

a controller for directing said signal to one of said first and second amplifier stages according to a predetermined threshold, wherein said controller comprises a first set of pin-diode switches in conjunction with quarter-wavelength lines for opening and closing a radio frequency input for said first amplifier stage.

8. The wireless communications network as set forth in claim 7, further comprising a second set of pin-diode switches in conjunction with quarter-wavelength lines for opening and closing said radio frequency input for said second amplifier stage.

9. The wireless communications network as set forth in claim 7, further comprising:

a time delay circuit for delaying a radio frequency input signal; and

a sampling circuit for determining the power level of said input signal.

10. The wireless communications network as set forth in claim 7, further comprising:

a detection circuit for sampling an incoming radio frequency signal to determine a power level of said signal; and

a switch for switching said radio frequency signal to one of said first amplifier stage and said second amplifier stage.

11. The wireless communications network as set forth in claim 7, further comprising a circuit for switching said incoming signal to said first amplifier stage for processing radio frequency signals below a predetermined power level.

12. The wireless communications network as set forth in claim 7, further comprising a circuit for switching said incoming signal to said second amplifier stage for processing said radio frequency signals above a predetermined power level.

13. For use in a base station of a wireless communications network, a method for improving power amplifier efficiency comprising the steps of:

receiving a signal to be amplified;

determining a power level of the signal;

comparing the signal power level to a predetermined threshold;

if the signal power level is below the predetermined threshold, passing the signal to a first amplifier stage utilizing a first set of quarter wave-length lines in conjunction with pin-diode switches; and

if the signal power level is above the predetermined threshold, passing the signal to a second amplifier stage.

14. The method for improving power amplifier efficiency as set forth in claim 13 further comprising the step of delaying the signal and determining the power of the input signal.

15. The method for improving power amplifier efficiency as set forth in claim 13 wherein the step of passing the signal to a second amplifier stage utilizes a second set of quarter wave-length lines in conjunction with pin-diode switches.

16. The method for improving power amplifier efficiency as set forth in claim 13 further comprising the step of switching the signal to the first amplifier stage for processing, responsive to a detected peak power component below a predetermined threshold.

17. The method for improving power amplifier efficiency as set forth in claim 13 further comprising the step of directing the signal to the second amplifier stage for processing, responsive to a detected peak power component above a predetermined threshold.